參數(shù)資料
型號(hào)： bq2012
廠商： Benchmark Technology Group
英文描述： Gas Gauge IC With Slow-Charge Control(Gas Gauge芯片（帶慢充電控制）)
中文描述： 氣體計(jì)IC緩慢充電控制（電量監(jiān)測(cè)計(jì)芯片（帶慢充電控制））
文件頁(yè)數(shù)： 2/20頁(yè)
文件大?。?/td> 188K
代理商： BQ2012
Pin Descriptions
LCOM
LEDcommonoutput
Open-drain output switches V
CC
to source
current for the LEDs. The switch is off dur-
ing initialization to allow reading of the soft
pull-up
or
pull-down
LCOM is also high impedance when the dis-
play is off.
program
resistors.
SEG
1
–
SEG
6
LED display segment outputs (dual func-
tion with PROG
1
–PROG
6
)
Each output may activate an LED to sink
the current sourced from LCOM.
PROG
1
–
PROG
2
Programmed full count selection inputs
(dual function with SEG
1
–SEG
2
)
These three-level input pins define the pro-
grammed full count (PFC) thresholds de-
scribed in Table 2.
PROG
3
–
PROG
4
Gas gauge rate selection inputs (dual
function with SEG
3
–SEG
4
)
These three-level input pins define the scale
factor described in Table 2.
PROG
5
Self-discharge rate selection (dual func-
tion with SEG
5
)
This three-level input pin defines the selfdis-
chargecompensationrateshowninTable1.
PROG
6
Display mode selection (dual function
with SEG
6
)
This three-level pin defines the display op-
eration shown in Table 1.
CHG
Charge control output
This open-drain output becomes active low
when charging is allowed.
conditions are described in the Charge Con-
trol section.
Valid charging
SR
Sense resistor input
The voltage drop (V
SR
) across the sense re-
sistor R
S
is monitored and integrated over
time to interpret charge and discharge activ-
ity. The SR input is tied to the high side of
the sense resistor. V
SR
< V
SS
indicates dis-
charge, and V
SR
> V
SS
indicates charge. The
effective voltage drop (V
SRO
) as seen by the
bq2012 is V
SR
+ V
OS
(see Table 5).
DISP
Display control input
DISP high disables the LED display. DISP
tied to V
CC
allows PROG
X
to connect directly
to V
CC
or V
SS
instead of through a pull-up or
pull-down resistor. DISP floating allows the
LED display to be active during a valid
charge or during discharge if the NAC regis-
ter is updated at a rate equivalent to V
SRO
≤
-4mV. DISP low activates the display. See
Table 1.
SB
Secondary battery input
This input monitors the single-cell voltage
potential through a high-impedance resis-
tive divider network for end-of-discharge
voltage (EDV) thresholds, maximum charge
voltage (MCV), and battery removed.
EMPTY
Battery empty output
This
impedance on detection of a valid end-of-
discharge voltage (V
EDVF
) and is low following
the next application of a valid charge.
open-drain
output
becomes
high-
DQ
Serial I/O pin
This is an open-drain bidirectional pin.
REF
Voltage reference output for regulator
REF provides a voltage reference output for
an optional micro-regulator.
V
CC
Supply voltage input
V
SS
Ground
2
bq2012
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