參數(shù)資料
型號(hào)： bq2012
廠商： Benchmark Technology Group
英文描述： Gas Gauge IC With Slow-Charge Control(Gas Gauge芯片（帶慢充電控制）)
中文描述： 氣體計(jì)IC緩慢充電控制（電量監(jiān)測(cè)計(jì)芯片（帶慢充電控制））
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 188K
代理商： BQ2012
The
battery removed
flag (BRM) is asserted whenever
the potential on the SB pin (relative to V
SS
) rises above
MCV or falls below 0.1V. The BRM flag is asserted until
the condition causing BRM is removed.
The BRM values are:
Where BRM is:
0
0.1V < V
SB
< 2.25V
1
0.1 V > V
SB
or V
SB
> 2.25V
The
capacity inaccurate
flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2012 is reset. The flag is cleared
after an LMD update.
The CI values are:
Where CI is:
0
When LMD is updated with a valid full dis-
charge
1
After the 64th valid charge action with no
LMD updates
The
valid discharge
flag (VDQ) is asserted when the
bq2012 is discharged from NAC = LMD.
mains set until either LMD is updated or one of three
actions that can clear VDQ occurs:
The flag re-
I
The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.
I
A valid charge action sustained at V
SRO
> V
SRQ
for at
least 256 NAC counts.
I
The EDV1 flag was set at a temperature below 0°C
The VDQ values are:
Where VDQ is:
0
SDCR
≥
4096, subsequent valid charge ac-
tion detected, or EDV1 is asserted with the
temperature less than 0°C
1
On first discharge after NAC = LMD
The
charge control
flag, CHG, is asserted whenever
the CHG pin is asserted (see the charge control section
on page 7 for a description of the CHG pin function).
The CHG values are:
Where CHG is:
0
When the CHG pin is asserted active low,
signifying that the bq2012 is in a state to
allow charge activity.
1
When the CHG pin is high-impedance, sig-
nifying that no charge activity should take
place.
The
first end-of-discharge warning
flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG
1
, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is immi-
nent. The EDV1 flag is latched until a valid charge has
been detected.
The EDV1 values are:
Where EDV1 is:
0
Valid charge action detected, V
SB
≥
1.05V
1
V
SB
< 1.05V providing that OVLD=0 (see
FLGS2 register description)
The
final end-of-discharge warning
flag (EDVF) flag
is used to warn that battery power is at a failure condi-
tion. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
EMPTY pin is also forced to a high-impedance state on
assertion of EDV1. The host system may pull EMPTY
high, which may be used to disable circuitry to prevent
deep-discharge of the battery.
12
bq2012
FLGS1 Bits
4
-
7
-
6
-
5
-
3
-
2
1
-
0
-
CHG
FLGS1 Bits
4
-
7
-
6
-
5
-
3
2
-
1
-
0
-
VDQ
FLGS1 Bits
4
-
7
-
6
-
5
-
3
-
2
-
1
0
-
EDV1
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
CI
-
-
-
-
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
BRM
-
-
-
-
-
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