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參數(shù)資料
| 型號： | BM29F400T-90TC |
| 英文描述： | x8/x16 Flash EEPROM |
| 中文描述： | x8/x16閃存EEPROM |
| 文件頁數(shù)： | 15/37頁 |
| 文件大?。?/td> | 265K |
| 代理商： | BM29F400T-90TC |
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BRIGHT
Microelectronics
Inc.
BM29F400T/BM29F400B
A Winbond Company
- 15 -
Publication Release Date: December 1999
Revision A2
During a programming operation, the RY/BY pin is driven low after the rising edge of the fourth WE
pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth
WE
pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to the timing
waveforms for the RY/BY status pin for further clarification. The RY/BY pin is high in the Standby
mode.
Since this is an open-drain output, several RY/BY pins can be tied together with a pull-up resistor to
Vcc.
RESET
Hardware Reset
The BM29F400 device may be RESET by driving the RESET pin to V
IL
. The RESET pin must be
kept low (V
IL
) for at least 500 nS. Pulling the
RESET
pin low will terminate any operation in progress.
The internal state machine will be RESET to the read mode 1 mS to 230 mS after the RESET pin is
driven low. If a hardware
RESET
occurs during a Programming or Erase operation, the data at that
particular location will be indeterminate.
When the RESET pin is low and the internal RESET is complete, the device goes to Standby mode
and cannot be accessed. Also, note that all the data output pins are tri-stated for the duration of the
RESET pulse. Once the RESET pin is taken high, the device requires 500 nS of wake up time until
outputs are valid for a read access.
The RESET pin may be tied to the system RESET input. Therefore, if a system RESET occurs
during an Internal Programming or Erase operation, the device will be automatically
RESET
to read
mode. This will enable the system's microprocessor to read the boot-up firmware from the Flag's
memory.
Data Protection
The BM29F400 is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power-up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out
for Vcc less than 3.2V (typically 3.7V). If Vcc < V
LKO
, the command register is disabled and all
internal programming/erase circuits are disabled. Under this condition the device will
RESET
to the
Read mode. Subsequent writes will be ignored until the Vcc level is greater than V
LKO
. It is the users
responsibility to ensure that the control pins are logically correct to prevent unintentional writes when
Vcc is above 3.2V.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 nS (typical) on
OE
,
CE
or
WE
will not initiate a write cycle.
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