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參數(shù)資料
| 型號： | AZP94XP |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | ECL/PECL ±1, ±2 Clock Generation Chip with Tristate Compatible Outputs |
| 中文描述： | ECL / PECL的± 1，± 2時鐘發(fā)生器芯片兼容的三態(tài)輸出 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 149K |
| 代理商： | AZP94XP |
AZP94
ECL/PECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
Green and RoHS Compliant / Lead (Pb)
Free Package Available
3.0V to 5.5V Operation
Selectable Divide Ratio
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Tristate Compatible Outputs
Input Buffer Powers Down when
Disabled
Selectable Input Biasing
High Bandwidth for
≥
1GHz
Available in a MLP 8 (2x2) Package
IBIS Model File Available on Arizona
Microtek Website
DESCRIPTION
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is
selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If
DIV-SEL is connected to V
EE
, it functions as a ÷2 divider.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), V
EE
, or
connected to V
EE
via a 20k
Ω
± 20% resistor. Leaving EN-SEL open or connecting it to V
EE
allows the EN pin/pad to
function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75k
Ω
pull-up resistor is selected
which enables the outputs whenever EN is left open. When EN-SEL is connected to V
EE
, an internal 75k
Ω
pull-
down resistor is selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to V
EE
with a 20k
Ω
resistor will allow the EN pin/pad to function as an active low
PECL/ECL enable with an internal 75k
Ω
pull-down resistor. In this mode, outputs are enabled when EN is left open
(NC). The default logic condition can be overridden by connecting the EN to V
CC
with an external resistor of
≤
20k
Ω
. If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to V
EE
with
a 20k
Ω
resistor), the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for
details.
When the AZP94 is disabled, the Q and Q outputs are forced LOW and the input buffer is powered down to
minimize feed through. This feature allows tristate compatible parallel output connections. Multiple AZP94 chip
outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled AZP94 can drive
the output lines without interference from the unselected units. In addition, the AZP94 can be used in parallel
connection with PECL/ECL parts whose outputs are high impedance when disabled.
The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when
the outputs are disabled.
PACKAGE AVAILABILITY
PART NO.
PACKAGE
MLP 8 (2x2) Green
/ RoHS Compliant
/ Lead (Pb) Free
DIE
MARKING
NOTES
AZP94NAG
J4G
<Date Code>
1,2
AZP94XP
N/A
3,4
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” for year followed by “WW” for week.
Waffle Pack, die thickness 180μ.
Contact factory for availability.
2
3
4
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| AZP96_12 | 制造商:AZM 制造商全稱:AZM 功能描述:PECL/ECL Differential Receiver |
| AZP96NG | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL Differential Receiver |
| AZPB.1X40 | 制造商:FACOM 功能描述:SCREWDRIVER PHILLIPS NO.1 |
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