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參數(shù)資料
| 型號(hào)： | AXDA2600DKV3D |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2083 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | OPGA-453 |
| 文件頁(yè)數(shù)： | 93/106頁(yè) |
| 文件大?。?/td> | 2275K |
| 代理商： | AXDA2600DKV3D |
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Chapter 11
Pin Descriptions
75
25175H—March 2003
AMD Athlon XP Processor Model 8 Data Sheet
Preliminary Information
CONNECT Pin
CONNECT is an input from the system used for power
management and clock-forward initialization at reset.
COREFB and
COREFB# Pins
COREFB and COREFB# are outputs to the system that provide
processor core voltage feedback to the system.
CPU_PRESENCE# Pin
CPU_PRESENCE# is connected to VSS on the processor
package. If pulled-up on the motherboard, CPU_PRESENCE#
may be used to detect the presence or absence of a processor in
the Socket A-style socket.
DBRDY and DBREQ#
Pins
DBRDY and DBREQ# are routed to the debug connector.
DBREQ# is tied to VCC_CORE with a pullup resistor.
FERR Pin
FERR is an output to the system that is asserted for any
unmasked numerical exception independent of the NE bit in
CR0. FERR is a push-pull active High signal that must be
inverted and level shifted to an active Low signal. For more
information about FERR and FERR#, see the “Required
Circuits” chapter of the AMD Athlon Processor-Based
Motherboard Design Guide, order# 24363.
FID[3:0] Pins
FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 26 on page 76 shows the encodings of the c lock
multipliers on FID[3:0].
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