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參數(shù)資料
| 型號： | AU5517DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP 2 CURRENT CTRL 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 跨導(dǎo) |
| 電路數(shù)： | 2 |
| 輸出類型： | 推挽式 |
| 轉(zhuǎn)換速率： | 50 V/µs |
| 增益帶寬積： | 2MHz |
| 電流 - 輸入偏壓： | 400nA |
| 電壓 - 輸入偏移： | 400µV |
| 電流 - 電源： | 2.6mA |
| 電流 - 輸出 / 通道： | 650µA |
| 電壓 - 電源，單路/雙路(±)： | 4 V ~ 44 V，±2 V ~ 22 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | AU5517DR2GOSCT |
NE5517, NE5517A, AU5517
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS (Note 4)
Characteristic
Test Conditions
Symbol
AU5517/NE5517
NE5517A
Unit
Min
Typ
Max
Min
Typ
Max
Input Offset Voltage
Overtemperature Range
IABC 5.0 mA
VOS
0.4
0.3
5.0
0.4
0.3
2.0
5.0
2.0
mV
DVOS/DT
Avg. TC of Input Offset Voltage
7.0
mV/°C
VOS Including Diodes
Diode Bias Current
(ID) = 500 mA
0.5
5
0.5
2.0
mV
Input Offset Change
5.0 mA ≤ IABC ≤ 500 mA
VOS
0.1
3.0
mV
Input Offset Current
IOS
0.1
0.6
0.1
0.6
mA
DIOS/DT
Avg. TC of Input Offset Current
0.001
mA/°C
Input Bias Current
Overtemperature Range
IBIAS
0.4
1.0
5.0
8.0
0.4
1.0
5.0
7.0
mA
DIB/DT
Avg. TC of Input Current
0.01
mA/°C
Forward Transconductance
Overtemperature Range
gM
6700
5400
9600
13000
7700
4000
9600
12000
mmho
gM Tracking
0.3
dB
Peak Output Current
RL = 0, IABC = 5.0 mA
RL = 0, IABC = 500 mA
RL = 0, Overtemperature
Range
IOUT
350
300
5.0
500
650
3.0
350
300
5.0
500
7.0
650
mA
Peak Output Voltage
Positive
Negative
RL = ∞, 5.0 mA ≤ IABC ≤ 500 mA
VOUT
+12
12
+14.2
14.4
+12
12
+14.2
14.4
V
Supply Current
IABC = 500 mA, both channels
ICC
2.6
4.0
2.6
4.0
mA
VOS Sensitivity
Positive
Negative
D VOS/D V+
D VOS/D V
20
150
20
150
mV/V
Common-mode Rejection
Ration
CMRR
80
110
80
110
dB
Common-mode Range
±12
±13.5
±12
±13.5
V
Crosstalk
Referred to Input (Note 5)
20 Hz < f < 20 kHz
100
dB
Differential Input Current
IABC = 0, Input = ±4.0 V
IIN
0.02
100
0.02
10
nA
Leakage Current
IABC = 0 (Refer to Test Circuit)
0.2
100
0.2
5.0
nA
Input Resistance
RIN
10
26
10
26
kW
Open-loop Bandwidth
BW
2.0
MHz
Slew Rate
Unity Gain Compensated
SR
50
V/ms
Buffer Input Current
5
INBUFFER
0.4
5.0
0.4
5.0
mA
Peak Buffer Output Voltage
5
VOBUFFER
10
V
DVBE of Buffer
Refer to Buffer VBE Test
Circuit (Note 6)
0.5
5.0
0.5
5.0
mV
4. These specifications apply for VS = ±15 V, Tamb = 25°C, amplifier bias current (IABC) = 500 mA, Pins 2 and 15 open unless otherwise
specified. The inputs to the buffers are grounded and outputs are open.
5. These specifications apply for VS = ±15 V, IABC = 500 mA, ROUT = 5.0 kW connected from the buffer output to VS and the input of the buffer
is connected to the transconductance amplifier output.
6. VS = ±15, ROUT = 5.0 kW connected from Buffer output to VS and 5.0 mA ≤ IABC ≤ 500 mA.
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