參數(shù)資料
型號: ATSAM3S8CA-CU
廠商: Atmel
文件頁數(shù): 24/57頁
文件大小: 0K
描述: IC MCU 512KB CORTEX-M3 100-BGA
標準包裝: 260
系列: SAM3S
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 64MHz
連通性: EBI/EMI,I²C,IrDA,MMC,SPI,SSC,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 79
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉換器: A/D 16x12b,D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
30
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
9.1.3.10
SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is
set to 0.
9.1.3.11
GPNVM Bits
The SAM3S8 features two GPNVM bits, whereas SAM3SD8 features three GPNVM bits. These
bits can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set
GPNVM Bit” of the EEFC User Interface.
The Flash of the SAM3S8 is composed of 512 Kbytes in a single bank, while the SAM3SD8
Flash is composed of dual banks, each containing 256 Kbytes. The dual-bank function enables
programming one bank while the other one is read (typically while the application code is run-
ning). Only one EEFC (Flash controller) controls the two banks. Note that it is not possible to
program simultaneously, or read simultaneously, the dual banks of the Flash.
The first bank of 256 Kbytes is called Bank 0 and the second bank of 256 Kbytes, Bank 1.
The SAM3SD8 embeds an additional GPNVM bit: GPNVM2.
9.1.4
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.
Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting
ERASE clears the GPNVM Bit 2 and thus selects the boot from bank 0 by default.
Table 9-2.
General-purpose Non volatile Memory Bits
GPNVMBit[#]
Function
0
Security bit
1
Boot mode selection
2
Bank selection (Bank 0 or Bank 1) Only on SAM3SD8
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