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鍨嬭櫉锛� ATMEGA48PA-MMN
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 193/448闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 4KB FLASH 20MHZ 28QFN
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 megaAVR Introduction
妯欐簴鍖呰锛� 490
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
閫i€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 23
绋嬪簭瀛樺劜鍣ㄥ閲忥細 4KB锛�2K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 256 x 8
RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 28-VFQFN 瑁搁湶鐒婄洡
鍖呰锛� 鎵樼洡
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272
8161D鈥揂VR鈥�10/09
ATmega48PA/88PA/168PA/328P
25.2.3
Preventing Flash Corruption
During periods of low V
CC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low V
CC reset protection circuit can be
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
2.
Keep the AVR core in Power-down sleep mode during periods of low V
CC. This will pre-
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
25.2.4
Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 26-6 shows the typical pro-
gramming time for Flash accesses from the CPU.
Note:
1. Minimum and maximum programming time is per individual operation.
Table 25-1.
SPM Programming Time
Symbol
Min Programming Time
Max Programming Time
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
3.7 ms
4.5 ms
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ATMEGA48PA-PN MCU AVR 4KB FLASH 20MHZ 28PDIP
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516-230-156 CONN COVER PLASTIC 56POS SIDE
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516-230-438 CONN COVER PLASTIC 38POS TOP
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ATMEGA48PA-MMNR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 4KB FL 256B EE 512B SRAM 20MHz 105C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
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ATMEGA48PA-MU 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 4KB FLASH 20 MHZ,IND TEMP RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
ATMEGA48PA-MU@SL383 鍒堕€犲晢:Atmel 鍔熻兘鎻忚堪:MCU 8-bit ATmega AVR RISC 4KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R