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鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 4KB FLASH 20MHZ 28QFN
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妯欐簴鍖呰锛� 490
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
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澶栧湇瑷倷锛� 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁革細 23
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绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
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RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁告摎杞夋彌鍣細 A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏ч儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 28-VFQFN 瑁搁湶鐒婄洡
鍖呰锛� 鎵樼洡
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204
8161D鈥揂VR鈥�10/09
ATmega48PA/88PA/168PA/328P
20. USART in SPI Mode
20.1
Features
Full Duplex, Three-wire Synchronous Data Transfer
Master Operation
Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
LSB First or MSB First Data Transfer (Configurable Data Order)
Queued Operation (Double Buffered)
High Resolution Baud Rate Generator
High Speed Operation (f
XCKmax = fCK/2)
Flexible Interrupt Generation
20.2
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation.
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
control logic is disabled. The USART RX and TX control logic is replaced by a common SPI
transfer control logic. However, the pin control logic and interrupt generation logic is identical in
both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the
control registers changes when using MSPIM.
20.3
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-
ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one
(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should
be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations, see Table 20-1:
鐩搁棞PDF璩囨枡
PDF鎻忚堪
ATMEGA48PA-PN MCU AVR 4KB FLASH 20MHZ 28PDIP
AT89LS51-16PU IC MCU 4K FLASH 16MHZ 40-DIP
516-230-156 CONN COVER PLASTIC 56POS SIDE
ATTINY44A-PU IC MCU AVR 4K FLASH 20MHZ 14PDIP
516-230-438 CONN COVER PLASTIC 38POS TOP
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