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鍙冩暩璩囨枡
鍨嬭櫉锛� ATMEGA48PA-MMN
寤犲晢锛� Atmel
鏂囦欢闋佹暩锛� 113/448闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 4KB FLASH 20MHZ 28QFN
鐢㈠搧鍩硅〒妯″锛� megaAVR Introduction
妯欐簴鍖呰锛� 490
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
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杓稿叆/杓稿嚭鏁革細 23
绋嬪簭瀛樺劜鍣ㄥ閲忥細 4KB锛�2K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 256 x 8
RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁告摎杞夋彌鍣細 A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏ч儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 28-VFQFN 瑁搁湶鐒婄洡
鍖呰锛� 鎵樼洡
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ATmega48PA/88PA/168PA/328P
7.4.2
Preventing EEPROM Corruption
During periods of low V
CC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an external low V
CC reset Protection circuit can
be used. If a reset occurs while a write operation is in progress, the write operation will be com-
pleted provided that the power supply voltage is sufficient.
7.5
I/O Memory
The I/O space definition of the ATmega48PA/88PA/168PA/328P is shown in 鈥漅egister Sum-
All ATmega48PA/88PA/168PA/328P I/Os and peripherals are placed in the I/O space. All I/O
locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
Refer to the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data
space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48PA/88PA/168PA/328P is a complex microcontroller with more peripheral units than
can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For
the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
7.5.1
General Purpose I/O Registers
The ATmega48PA/88PA/168PA/328P contains three General Purpose I/O Registers. These
registers can be used for storing any information, and they are particularly useful for storing
global variables and Status Flags. General Purpose I/O Registers within the address range 0x00
- 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
ATMEGA48PA-PN MCU AVR 4KB FLASH 20MHZ 28PDIP
AT89LS51-16PU IC MCU 4K FLASH 16MHZ 40-DIP
516-230-156 CONN COVER PLASTIC 56POS SIDE
ATTINY44A-PU IC MCU AVR 4K FLASH 20MHZ 14PDIP
516-230-438 CONN COVER PLASTIC 38POS TOP
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