153
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Figure 17-8. Timer/Counter Timing diagram, no prescaling.
Figure 17-9. Timer/Counter Timing diagram, with prescaler (f
clk_I/O/8).
Figure 17-10. Timer/Counter Timing diagram, setting of OCF2A, with prescaler (f
clk_I/O/8).
clk
Tn
(clk
I/O/1)
TOVn
clk
I/O
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O/8)
