參數(shù)資料
型號： ATMEGA324PA-PU
廠商： Atmel
文件頁數(shù)： 21/160頁
文件大?。?/td> 0K
描述： MCU AVR 32KB FLASH 40PDIP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
megaAVR Introduction
標準包裝： 10
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： ATSTK600-RC05-ND - STK600 ROUTING CARD AVR
ATSTK600-ND - DEV KIT FOR AVR/AVR32
117
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
16.5
Prescaler Reset
The prescaler is free running, that is, operates independently of the clock select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the
Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care must
be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A pres-
caler reset will affect the prescaler period for all Timer/Counters it is connected to.
16.6
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 16-2 shows a block diagram of the counter and its surroundings.
Figure 16-2. Counter unit block diagram.
Signal description (internal signals):
Count
Increment or decrement TCNTn by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNTn (set all bits to zero).
clk
Tn
Timer/Counter clock.
TOP
Signalize that TCNTn has reached maximum value.
BOTTOM
Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-
taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight
bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNTnH value when the TCNTnL is read, and
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit)
TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP
BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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