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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ATMEGA16HVA-4CKU |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 25/196闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU AVR 16K FLASH 4MHZ 36-LGA |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | MCU Product Line Introduction megaAVR Introduction |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 364 |
| 绯诲垪锛� | AVR® ATmega |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 閫ｉ€氭€э細 | SPI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 7 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 512 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 9 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 5x12b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -20°C ~ 85°C |
| 灏佽/澶栨锛� | 36-LGA |
| 鍖呰锛� | 鎵樼洡(p谩n) |
| 閰嶇敤锛� | ATSTK600-ND - DEV KIT FOR AVR/AVR32 ATSTK500-ND - PROGRAMMER AVR STARTER KIT |
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120
8024A鈥揂VR鈥�04/08
ATmega8HVA/16HVA
22. Voltage Regulator
22.1
Features
3.3V fixed output voltage
Automatic selection of Step-up or Linear Regulation depending on VFET voltage.
Fixed Linear Regulation mode can be selected for 2-cell applications
Battery Pack Short mode allowing large voltage drop at VFET without pulling VREG low.
22.2
Overview
The Voltage Regulator is a Combined Step-up and Linear Voltage Regulator. This allows the
same Voltage Regulator module to be used efficiently for a large range of input voltages.
A built in Charge-pump with external capacitors is combined with a linear regulator to keep a
constant output voltage for input voltages in the range 1.8 - 9.0V.
Figure 22-1 on page 121 shows the Voltage Regulator block diagram with external components
for combined Step-up and Linear mode. Figure 22-2 on page 121 shows the regulated voltage
VREG as a function of the input voltage VFET for 1-cell operation. When the VFET is sufficiently
high, the regulator switches automatically to linear operation. When VFET drops below a certain
level the regulator automatically switch back to step-up regulation. The different reset sources
during initialisation and shut down is also shown.
Figure 22-3 on page 122 shows the Voltage Regulator block diagram with external components
for Linear mode only, intended for 2-cell applications. In Linear mode only, the input voltage
range is 3.6 - 9.0V. In this case, no external fly capacitors are needed, and CF1N should be
grounded. Figure 22-4 on page 122 illustrates this operation.
In case of battery pack shortening, the voltage at the input of the regulator will drop quickly. If it
drops below minimum operating voltage, the voltage regulator can no longer supply internal or
external circuitry. However, the output voltage will not be pulled down by this incident, and the
external CREG capacitor can supply the circuitry for a time given by the size of the capacitor and
the total current consumption during the same period. VREG must stay above the Brown-Out
Threshold to avoid BOD reset. If a battery pack short occurs when VREG is equal to 3.3V and
the BOD level is 2.9V, the chip can continue operation for a time given by:
where I
AVG represents the average current drawn from CREG. For CREG = 2.2 F and
I
AVG = 100 A, this time equals 8.8 ms. The Voltage Regulator Monitor will detect if a short-circuit
has occured, allowing SW to minimize I
AVG.
When charging deeply over-discharged cells, the FET Driver will be operated in Deep Under-
Voltage Recovery (DUVR) mode. See 鈥淔ET Driver鈥� on page 136. In this mode a suitable voltage
drop is developed across the Charge FET to ensure proper operating voltage at the VFET pin.
This will ensure normal operation of the chip during 0-volt charging without setting the charger in
quick-charge mode before the cell has reached a safe cell voltage.
t
c
螖v
I
AVG
------------
CREG 0.4V
I
AVG
---------------------------------
==
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| VE-B30-IY-F1 | CONVERTER MOD DC/DC 5V 50W |
| VJ1825Y123JBCAT4X | CAP CER 0.012UF 200V 5% X7R 1825 |
| VJ1825Y123JBEAT4X | CAP CER 0.012UF 500V 5% X7R 1825 |
| VJ1825Y183JBCAT4X | CAP CER 0.018UF 200V 5% X7R 1825 |
| ATMEGA329-16AU | IC AVR MCU 32K 16MHZ 64TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ATMEGA16HVA-4CKUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR batman 16KB FLSH 4 MHZ,LGA,GRN1.8-9V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA16HVA-4TU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16KB Flash Memory 1.8V - 9.0V Supply RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA16HVA-4TUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR batman 16KB FLSH 4 MHZ TSOP, 1.8-9V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA16HVB | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū(ch膿ng):ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 16K/32K Bytes In-System Programmable Flash |
| ATMEGA16HVB_09 | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū(ch膿ng):ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 16K/32K Bytes In-System Programmable Flash |
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