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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ATMEGA16HVA-4CKU |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 16/196闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU AVR 16K FLASH 4MHZ 36-LGA |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | MCU Product Line Introduction megaAVR Introduction |
| 妯欐簴鍖呰锛� | 364 |
| 绯诲垪锛� | AVR® ATmega |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 閫ｉ€氭€э細 | SPI |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 7 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 512 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 9 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 5x12b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -20°C ~ 85°C |
| 灏佽/澶栨锛� | 36-LGA |
| 鍖呰锛� | 鎵樼洡 |
| 閰嶇敤锛� | ATSTK600-ND - DEV KIT FOR AVR/AVR32 ATSTK500-ND - PROGRAMMER AVR STARTER KIT |
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112
8024A鈥揂VR鈥�04/08
ATmega8HVA/16HVA
20. Voltage ADC 鈥� 5-channel General Purpose 12-bit Sigma-Delta ADC
20.1
Features
12-bit Resolution
519s Conversion Time @ 1 MHz clk
VADC
Two Differential Input Channels for Cell Voltage Measurements
Three Single Ended Input Channels
0.2x Pre-scaling of Cell Voltages
Interrupt on V-ADC Conversion Complete
20.2
Overview
The ATmega8HVA/16HVA features a 12-bit Sigma-Delta ADC.
The Voltage ADC (V-ADC) is connected to five different sources through the Input Multiplexer.
There are two differential channels for Cell Voltage measurements. These channels are scaled
0.2x to comply with the Full Scale range of the V-ADC. In addition there are three single ended
channels referenced to SGND. One channel is for measuring the internal temperature sensor
VPTAT and two channels for measuring the voltage at ADC0 and ADC1.
When the V-ADC is not used, power consumption can be minimized by writing the PRVADC bit
in PRR0 to one. See 鈥漃RR0 鈥� Power Reduction Register 0鈥� on page 39 for details on how to use
the PRVADC bit.
Figure 20-1. Voltage ADC Block Schematic
20.3
Operation
To enable V-ADC conversions, the V-ADC Enable bit, VADEN, in V-ADC Control and Status
Register 鈥� VADCSR must be set. If this bit is cleared, the V-ADC will be switched off, and any
ongoing conversions will be terminated. The V-ADC is automatically disabled in Power-save and
V-ADC CONVERSION COMPLETE IRQ
8-BIT DATA BUS
V-ADC MULTIPLEXER
SEL. REG (VADMUX)
V-ADC CONTROL AND
STATUS REG (VADCSR)
V-ADC DATA REGISTER
(VADCL/ADCH)
VADCCIE
VADCCIF
12-BIT
SIGMA-DELTA ADC
INPUT
MUX
V-ADC CONTROL
ADC1
ADC0
VTEMP
PV2
PV1
NV
Note:
The shaded signals are scaled by 0.2,
other signals are scaled by 1.0
VREF
SGND
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VE-B30-IY-F1 | CONVERTER MOD DC/DC 5V 50W |
| VJ1825Y123JBCAT4X | CAP CER 0.012UF 200V 5% X7R 1825 |
| VJ1825Y123JBEAT4X | CAP CER 0.012UF 500V 5% X7R 1825 |
| VJ1825Y183JBCAT4X | CAP CER 0.018UF 200V 5% X7R 1825 |
| ATMEGA329-16AU | IC AVR MCU 32K 16MHZ 64TQFP |
鐩搁棞浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ATMEGA16HVA-4CKUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR batman 16KB FLSH 4 MHZ,LGA,GRN1.8-9V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATMEGA16HVA-4TU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16KB Flash Memory 1.8V - 9.0V Supply RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATMEGA16HVA-4TUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR batman 16KB FLSH 4 MHZ TSOP, 1.8-9V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATMEGA16HVB | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 16K/32K Bytes In-System Programmable Flash |
| ATMEGA16HVB_09 | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 16K/32K Bytes In-System Programmable Flash |
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