鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ATMEGA16HVA-4CKU
寤犲晢锛� Atmel
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 16/196闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 16K FLASH 4MHZ 36-LGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� MCU Product Line Introduction
megaAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 364
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 4MHz
閫ｉ€氭€э細 SPI
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝POR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 7
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 16KB锛�8K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 256 x 8
RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 9 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 5x12b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -20°C ~ 85°C
灏佽/澶栨锛� 36-LGA
鍖呰锛� 鎵樼洡
閰嶇敤锛� ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATSTK500-ND - PROGRAMMER AVR STARTER KIT
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112
8024A鈥揂VR鈥�04/08
ATmega8HVA/16HVA
20. Voltage ADC 鈥� 5-channel General Purpose 12-bit Sigma-Delta ADC
20.1
Features
12-bit Resolution
519s Conversion Time @ 1 MHz clk
VADC
Two Differential Input Channels for Cell Voltage Measurements
Three Single Ended Input Channels
0.2x Pre-scaling of Cell Voltages
Interrupt on V-ADC Conversion Complete
20.2
Overview
The ATmega8HVA/16HVA features a 12-bit Sigma-Delta ADC.
The Voltage ADC (V-ADC) is connected to five different sources through the Input Multiplexer.
There are two differential channels for Cell Voltage measurements. These channels are scaled
0.2x to comply with the Full Scale range of the V-ADC. In addition there are three single ended
channels referenced to SGND. One channel is for measuring the internal temperature sensor
VPTAT and two channels for measuring the voltage at ADC0 and ADC1.
When the V-ADC is not used, power consumption can be minimized by writing the PRVADC bit
in PRR0 to one. See 鈥漃RR0 鈥� Power Reduction Register 0鈥� on page 39 for details on how to use
the PRVADC bit.
Figure 20-1. Voltage ADC Block Schematic
20.3
Operation
To enable V-ADC conversions, the V-ADC Enable bit, VADEN, in V-ADC Control and Status
Register 鈥� VADCSR must be set. If this bit is cleared, the V-ADC will be switched off, and any
ongoing conversions will be terminated. The V-ADC is automatically disabled in Power-save and
V-ADC CONVERSION COMPLETE IRQ
8-BIT DATA BUS
V-ADC MULTIPLEXER
SEL. REG (VADMUX)
V-ADC CONTROL AND
STATUS REG (VADCSR)
V-ADC DATA REGISTER
(VADCL/ADCH)
VADCCIE
VADCCIF
12-BIT
SIGMA-DELTA ADC
INPUT
MUX
V-ADC CONTROL
ADC1
ADC0
VTEMP
PV2
PV1
NV
Note:
The shaded signals are scaled by 0.2,
other signals are scaled by 1.0
VREF
SGND
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VE-B30-IY-F1 CONVERTER MOD DC/DC 5V 50W
VJ1825Y123JBCAT4X CAP CER 0.012UF 200V 5% X7R 1825
VJ1825Y123JBEAT4X CAP CER 0.012UF 500V 5% X7R 1825
VJ1825Y183JBCAT4X CAP CER 0.018UF 200V 5% X7R 1825
ATMEGA329-16AU IC AVR MCU 32K 16MHZ 64TQFP
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