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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ATMEGA16HVA-4CKU
寤犲晢锛� Atmel
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鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� MCU Product Line Introduction
megaAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 364
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
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绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 256 x 8
RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 9 V
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ATSTK500-ND - PROGRAMMER AVR STARTER KIT
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46
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ATmega8HVA/16HVA
11.3
Watchdog Timer
11.3.1
Features
Clocked from separate On-chip Oscillator
3 Operating modes
鈥揑nterrupt
鈥� System Reset
鈥� Interrupt and System Reset
Selectable Time-out period from 16 ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
11.3.2
Overview
ATmega8HVA/16HVA has an Enhanced Watchdog Timer (WDT). The WDT counts cycles of the
Ultra Low Power RC Oscillator. The WDT gives an interrupt or a system reset when the counter
reaches a given time-out value. In normal operation mode, it is required that the system uses the
WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is
reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.
Figure 11-6. Watchdog Timer
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-
tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alter-
ations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE
and changing time-out configuration is as follows:
Ultra Low Power RC
OSCILLATOR
16
ms
32
ms
64
ms
0.13s
0.26s
0.51s
1.0s
2.0s
4.1s
8.2s
WDP0
WDP1
WDP2
WDP3
WATCHDOG
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VE-B30-IY-F1 CONVERTER MOD DC/DC 5V 50W
VJ1825Y123JBCAT4X CAP CER 0.012UF 200V 5% X7R 1825
VJ1825Y123JBEAT4X CAP CER 0.012UF 500V 5% X7R 1825
VJ1825Y183JBCAT4X CAP CER 0.018UF 200V 5% X7R 1825
ATMEGA329-16AU IC AVR MCU 32K 16MHZ 64TQFP
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