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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ATMEGA16HVA-4CKU |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 138/196闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU AVR 16K FLASH 4MHZ 36-LGA |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | MCU Product Line Introduction megaAVR Introduction |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 364 |
| 绯诲垪锛� | AVR® ATmega |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 閫ｉ€氭€э細 | SPI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 7 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 512 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 9 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 5x12b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -20°C ~ 85°C |
| 灏佽/澶栨锛� | 36-LGA |
| 鍖呰锛� | 鎵樼洡 |
| 閰嶇敤锛� | ATSTK600-ND - DEV KIT FOR AVR/AVR32 ATSTK500-ND - PROGRAMMER AVR STARTER KIT |
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46
8024A鈥揂VR鈥�04/08
ATmega8HVA/16HVA
11.3
Watchdog Timer
11.3.1
Features
Clocked from separate On-chip Oscillator
3 Operating modes
鈥揑nterrupt
鈥� System Reset
鈥� Interrupt and System Reset
Selectable Time-out period from 16 ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
11.3.2
Overview
ATmega8HVA/16HVA has an Enhanced Watchdog Timer (WDT). The WDT counts cycles of the
Ultra Low Power RC Oscillator. The WDT gives an interrupt or a system reset when the counter
reaches a given time-out value. In normal operation mode, it is required that the system uses the
WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is
reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.
Figure 11-6. Watchdog Timer
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, the WDT gives a reset when the timer
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-
rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-
tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt
mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alter-
ations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE
and changing time-out configuration is as follows:
Ultra Low Power RC
OSCILLATOR
16
ms
32
ms
64
ms
0.13s
0.26s
0.51s
1.0s
2.0s
4.1s
8.2s
WDP0
WDP1
WDP2
WDP3
WATCHDOG
RESET
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| VE-B30-IY-F1 | CONVERTER MOD DC/DC 5V 50W |
| VJ1825Y123JBCAT4X | CAP CER 0.012UF 200V 5% X7R 1825 |
| VJ1825Y123JBEAT4X | CAP CER 0.012UF 500V 5% X7R 1825 |
| VJ1825Y183JBCAT4X | CAP CER 0.018UF 200V 5% X7R 1825 |
| ATMEGA329-16AU | IC AVR MCU 32K 16MHZ 64TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ATMEGA16HVA-4CKUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR batman 16KB FLSH 4 MHZ,LGA,GRN1.8-9V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA16HVA-4TU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16KB Flash Memory 1.8V - 9.0V Supply RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA16HVA-4TUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR batman 16KB FLSH 4 MHZ TSOP, 1.8-9V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA16HVB | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 16K/32K Bytes In-System Programmable Flash |
| ATMEGA16HVB_09 | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 16K/32K Bytes In-System Programmable Flash |
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