參數(shù)資料
型號(hào)： ATAM893T-TKSYD
廠商： Atmel
文件頁數(shù)： 85/98頁
文件大?。?/td> 0K
描述： IC MCU FLASH 4K MTP 20SSOP
標(biāo)準(zhǔn)包裝： 830
系列： MARC4
核心處理器： MARC4
芯體尺寸： 4-位
速度： 4MHz
連通性： SSI（2 線，3 線）
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類型： EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量： 256 x 4
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 6.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 20-SOIC（0.209"，5.30mm 寬）
包裝： 管件
86
4680C–4BMCU–01/05
ATAM893-D
6.1.2
Control Byte Format
6.2
EEPROM
The EEPROM has a size of 2
× 512 bits and is organized as 32 x 16-bit matrix each. To read
and write data to and from the EEPROM the serial interface must be used. The interface sup-
ports one and two byte write accesses and one to n-byte read accesses to the EEPROM.
6.2.1
EEPROM - Operating Modes
The operating modes of the EEPROM are defined via the control byte. The control byte contains
the row address, the mode control bits and the read/not-write bit that is used to control the direc-
tion of the following transfer. A 0 defines a write access and a 1 a read access. The five address
bits select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the
complete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or over-
written via the serial interface. The two mode control bits C
1 and C2 define in which order the
accesses to the buffer are performed: High byte – low byte or low byte – high byte. The
EEPROM also supports auto increment and auto decrement read operations.
After sending the start address with the corresponding mode, consecutive memory cells can be
read row by row without transmission of the row addresses.
Two special control bytes enable the complete initialization of EEPROM with 0 or with 1.
6.2.2
Write Operations
The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START
condition followed by a write control byte and one or two data bytes from the master. It is com-
pleted via the STOP condition from the master after the acknowledge cycle.
The programming cycle consists of an erase cycle (write “zeros”) and the write cycle (write
“ones”). Both cycles together take about 10 ms.
6.2.2.1
Acknowledge Polling
If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will
not acknowledge until the write cycle is finished. This can be used to detect the end of the write
cycle. The master must acknowledge polling by sending a start condition followed by the control
byte. If the device is still busy with the write cycle, it will not return an acknowledge and the mas-
ter has to generate a stop condition or perform further acknowledge polling sequences. If the
cycle is complete, it returns an acknowledge and the master can proceed with the next read or
write cycle.
EEPROM Address
Mode Control Bits
Read/
Write
Start
A4
A3
A2
A1
A0
C1
C0
R/NW
Acne
Start
Control byte
Acne
Data byte
Acne
Data byte
Acne
Stop
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