參數(shù)資料
型號(hào)： ATAM893T-TKSYD
廠商： Atmel
文件頁數(shù)： 42/98頁
文件大?。?/td> 0K
描述： IC MCU FLASH 4K MTP 20SSOP
標(biāo)準(zhǔn)包裝： 830
系列： MARC4
核心處理器： MARC4
芯體尺寸： 4-位
速度： 4MHz
連通性： SSI（2 線，3 線）
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類型： EEPROM
EEPROM 大小： 64 x 16
RAM 容量： 256 x 4
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 6.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 20-SOIC（0.209"，5.30mm 寬）
包裝： 管件
47
4680C–4BMCU–01/05
ATAM893-D
5.3.3
Timer 3
5.3.3.1
Features
Two Compare Registers
Capture Register
Edge Sensitive Input with Zero Cross Detection Capability
Trigger and Single Action Modes
Output Control Modes
Automatic Modulation and Demodulation Modes
FSK Modulation
Pulse width Modulation (PWM)
Manchester Demodulation Together with SSI
Bi-phase Demodulation Together with SSI
Pulse-width Demodulation Together with SSI
Figure 5-24. Timer 3
Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The
timer can be used as event counter, timer and signal generator. Its output can be programmed
as modulator and demodulator for the serial interface. The two compare registers enable various
modes of signal generation, modulation and demodulation. The counter can be driven by inter-
nal and external clock sources. For external clock sources, it has a programmable edge-
sensitive input which can be used as counter input, capture signal input or trigger input. This
timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core
→sleep and OSC-Stop →yes), this timer input is stopped too. The counter is readable via its
capture register while it is running. In capture mode, the counter value can be captured by a pro-
grammable capture event from the Timer 3 input or Timer 2 output.
8-bit Counter 3
RES
Compare 3/1
T3CO1
T3CP
T3CO2
Control
T3O
CL3
T3I
T3EX
SYSCL
T1OUT
POUT
I/O-bus
Compare 3/2
T3CM1
T3CM2
T3C
T3ST
Modulator 3
Demodu-
lator 3
M2
Control
SO
TOG3
INT5
RES
CM31
T3I
T3EX
TOG2
SI
SCI
T3M
T3CS
I/O-bus
Timer 2
SSI
CP3
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