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參數(shù)資料
| 型號： | ATAM893T-TKSYD |
| 廠商： | Atmel |
| 文件頁數(shù)： | 64/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 4K MTP 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 830 |
| 系列： | MARC4 |
| 核心處理器： | MARC4 |
| 芯體尺寸： | 4-位 |
| 速度： | 4MHz |
| 連通性： | SSI（2 線，3 線） |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器容量： | 4KB（4K x 8） |
| 程序存儲器類型： | EEPROM |
| EEPROM 大小： | 64 x 16 |
| RAM 容量： | 256 x 4 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 6.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 20-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
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4680C–4BMCU–01/05
ATAM893-D
Figure 5-44. MCL Bus Protocol 1
Bus not busy (1)
Both data and clock lines remain HIGH.
Start data transfer (2)
A HIGH to LOW transition of the SD line while the clock (SC)
is HIGH defines a START condition.
Stop data transfer (3)
A LOW to HIGH transition of the SD line while the clock (SC)
is HIGH defines a STOP condition.
Data valid (4)
The state of the data line represents valid data when,
after START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
Acknowledge
All address and data words are serially transmitted to and
from the device in eight-bit words. The receiving device
returns a zero on the data line during the ninth clock cycle to
acknowledge word receipt.
Figure 5-45. MCL Bus Protocol 2
5.3.4.8
SSI Interrupt
The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e., transmit
buffer empty or receive buffer full), the end of SSI data telegram or on the falling edge of the
SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed by the Interrupt Function
control bit (IFN). The SSI interrupt is usually used to synchronize the software control of the SSI
and inform the controller of the present SSI status. The Port 4 interrupts can be used together
with the SSI or, if the SSI itself is not required, as additional external interrupt sources. In either
case this interrupt is capable of waking the controller out of sleep mode.
To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Inter-
rupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits in
P4CR register.
(2)
(1)
(4)
(3)
(1)
Start
condition
Data
valid
Data
change
Data
valid
Stop
condition
SC
SD
SC
SD
Start
1n8
9
1st Bit
8th Bit
ACK
Stop
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATAM893X-TKHYZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Flash Version for ATAR080, ATAR090/890 and ATAR092/892 |
| ATAM893X-TKQYZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Flash Version for ATAR080, ATAR090/890 and ATAR092/892 |
| ATAM893X-TKSYZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Flash Version for ATAR080, ATAR090/890 and ATAR092/892 |
| ATAM894 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8k-flash Microcontroller |
| ATAM894P | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:MARC4 4-bit Microcontrollers |
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