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參數(shù)資料
| 型號(hào)： | AT91M40008 |
| 廠商： | Atmel Corp. |
| 英文描述： | Incorporates the ARM7TDMI⑩ ARM?? Thumb?? Processor Core |
| 中文描述： | 采用了ARM的ARM7TDMI的⑩？？拇指？？處理器核心 |
| 文件頁(yè)數(shù)： | 9/19頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | AT91M40008 |
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AT91R40008
1732CS
–
ATARM
–
02/02
JTAG/ICE Debug
ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. The pins
TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host
computer via the external ICE interface.
In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the
microcontroller. This is not fully IEEE1149.1 compliant.
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the
internal 32-bit address bus and defines three address spaces:
Internal memories in the four lowest megabytes
Middle space reserved for the external devices (memory or peripherals) controlled by the
EBI
Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in Little-endian mode only.
Internal Memories
The AT91R40008 microcontroller integrates 256K bytes of internal SRAM. All internal memo-
ries are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word
(32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or ARM
instructions is supported and internal memory can store twice as many Thumb instructions as
ARM ones.
The SRAM is mapped at address 0x0 (after the Remap command), allowing ARM7TDMI
exception vectors between 0x0 and 0x20 to be modified by the software.
Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcon-
troller performance and minimizes the system power consumption. The 32-bit bus increases
the effectiveness of the use of the ARM instruction set and the ability of processing data that is
wider than 16-bit, thus making optimal use of the ARM7TDMI advanced performance.
Being able to dynamically update application software in the 256-Kbyte SRAM adds an extra
dimension to the AT91R40008.
Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of the
NRST selects the type of boot memory (see Table 3).
The BMS pin is multiplexed with the I/O line P24, which can be programmed after reset like
any standard PIO line.
Table 3.
Boot Mode Select
BMS
Boot Memory
1
External 8-bit memory on NCS0
0
External 16-bit memory on NCS0
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| AT91M40100 | ARM THUMB - Based Microcontroller(基于ARM THUMB的微控制器) |
| AT91M40403 | ARM THUMB - Based Microcontroller(基于ARM THUMB的微控制器) |
| AT91F40416 | ARM THUMB - Based Microcontroller(基于ARM THUMB的微控制器) |
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相關(guān)代理商/技術(shù)參數(shù) |
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| AT91M40400 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M40400_99 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT91 ARM Thumb Microcontrollers |
| AT91M40400-25AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microcontroller |
| AT91M40400-25AI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microcontroller |
| AT91M40400-33AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microcontroller |
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