參數(shù)資料
型號: AT90S8515-8JC
廠商: Atmel
文件頁數(shù): 61/112頁
文件大?。?/td> 0K
描述: IC MCU 8K FLSH 8MHZ 44PLCC
標準包裝: 27
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
52
AT90S8515
0841G–09/01
UART
The AT90S8515 features a full duplex (separate receive and transmit registers) Univer-
sal Asynchronous Receiver and Transmitter (UART). The main features are:
Baud Rate Generator that can Generate a large Number of Baud Rates (bps)
High Baud Rates at Low XTAL Frequencies
8 or 9 Bits Data
Noise Filtering
Overrun Detection
Framing Error Detection
False Start Bit Detection
Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Data Transmission
A block schematic of the UART transmitter is shown in Figure 38.
Figure 38. UART Transmitter
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register, UDR. Data is transferred from UDR to the Transmit shift register when:
A new character has been written to UDR after the stop bit from the previous
character has been shifted out. The shift register is loaded immediately.
A new character has been written to UDR before the stop bit from the previous
character has been shifted out. The shift register is loaded when the stop bit of the
character currently being transmitted has been shifted out.
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