參數(shù)資料
型號: AT90S8515-8JC
廠商: Atmel
文件頁數(shù): 50/112頁
文件大?。?/td> 0K
描述: IC MCU 8K FLSH 8MHZ 44PLCC
標準包裝: 27
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 內部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
42
AT90S8515
0841G–09/01
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip oscillator that runs at 1 MHz.
This is the typical value at V
CC = 5V. See characterization data for typical values at other
V
CC levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval
can be adjusted (see Table 14 for a detailed description). The WDR (Watchdog Reset)
instruction resets the Watchdog Timer. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another
Watchdog reset, the AT90S8515 resets and executes from the reset vector. For timing
details on the Watchdog reset, refer to page 25.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 33. Watchdog Timer
Watchdog Timer Control
Register – WDTCR
Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90S8515 and will always read as zero.
Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be
followed:
Bit
765
4
321
0
$21 ($41)
WDTOE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R/W
Initial Value
0
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