參數(shù)資料
型號: AT90S8515-8JC
廠商: Atmel
文件頁數(shù): 34/112頁
文件大小: 0K
描述: IC MCU 8K FLSH 8MHZ 44PLCC
標(biāo)準(zhǔn)包裝: 27
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 8KB(4K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
28
AT90S8515
0841G–09/01
Timer/Counter Interrupt Flag
Register – TIFR
Bit 7 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, TOIE1
(T i m er /Counter 1 O v erfl ow Inte rr upt Enabl e) and T OV 1 ar e s e t ( one ), the
Timer/Counter1 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter1 changes counting direction at $0000.
Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A
(Timer/Counter1 Compare Match InterruptA Enable) and the OCF1A are set (one), the
Timer/Counter1 CompareA Match interrupt is executed.
Bit 5 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1B
(Timer/Counter1 Compare Match InterruptB Enable) and the OCF1B are set (one), the
Timer/Counter1 CompareB Match interrupt is executed.
Bit 4 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8515 and always reads zero.
Bit 3 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the
Timer/Counter1 value has been transferred to the input capture register (ICR1). ICF1 is
cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TICIE1
(Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture interrupt is executed.
Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8515 and always reads zero.
Bit 1 – TOV: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0
(T i m er /Counter 0 O v erfl ow Inte rr upt Enabl e) and T OV 0 ar e s e t ( one ), the
Timer/Counter0 Overflow interrupt is executed.
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8515 and always reads zero.
Bit
7
6
5
4
3
2
1
0
$38 ($58)
TOV1
OCF1A
OCIFB
ICF1
TOV0
TIFR
Read/Write
R/W
R
R/W
R
R/W
R
Initial Value
0
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