參數(shù)資料
型號(hào)： AT89EB5114-TGSIL
廠商： Atmel
文件頁(yè)數(shù)： 60/86頁(yè)
文件大小： 0K
描述： IC 8051 MCU FLASH 4K 20SOIC
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 38
系列： 89EB
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 11
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 616 (CN2011-ZH PDF)
63
AT89/83EB5114
4311C–8051–02/08
How to Take Advantage of the Calibration Value
The coefficient stored on the stacked die allow to determine the conversion result the
AT8xEB5114 should have returned in case its Vref was exactly equal to 2.4V. In order to
determine it, a multiplication of the result of the conversion with the coefficient stored in
the stack, followed by a shift are sufficient.
Example
Vref is 2.36V instead of 2.4V, and only 8 bits are necessary.
The value measured during the test 2.36V. So, in accordance with the Table 47, the
coefficient which has to be stored on the EEPROM is 0x7e which corresponds to
0.1111110 in binary, which also corresponds to around 2.36/2.4.
If, for example, after a conversion, the ADDH register contains 0xf0, to know the result
the ADC should have returned in case the Vref was really at 2.4V, the following opera-
tions are necessary:
0xf0 * 0x7e = 1111 0000 * 0111 1110 = 0x7620 = 0111 0110 0010 0000.
So because of the point on the coefficient, the result is 1110 110 which is 0xec.
Assembler code example
This is an example of assembler code optimized for size and fast recalculation in case 8
bits are sufficient.
start_adjustement :
MOV
B,coeff ; Coeff
MOV
A,ADDH
; ADC result
MUL
AB
;
RLC
A
; Recover lowest bit
MOV
A,B
;
RLC
A
; Recover result
JNC
end_fix ; Result OK
MOV
A,#0ffh ; Overflow
end_adjustement
:
RET
The new result is stored on the accumulator.
This routine requires 15 bytes + 3 bytes for the long call (LCALL).
The execution of the subroutine (including the LCALL) is 18 cycles in normal case and
19 cycles in case of overflow (less than 10us with a 12 MHz oscillator and the X2 mode).
Registers
Table 48. ADCON Register
ADCON (S:F3h)
ADC Control Register
7
6
5
4
3
2
1
0
QUIETM
PSIDLE
ADEN
ADEOC
ADSST
SCH2
SCH1
SCH0
Bit
Number
Bit
Mnemonic Description
7
QUIETM
Quiet mode (best precision)
Set to put in quiet mode during conversion.
Cleared by hardware after completion of the conversion.
6
PSIDLE
Pseudo Idle mode (good precision)
Set to put in idle mode during conversion.
Cleared by hardware after completion of the conversion.
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