參數(shù)資料
型號: AT89EB5114-TGSIL
廠商: Atmel
文件頁數(shù): 5/86頁
文件大小: 0K
描述: IC 8051 MCU FLASH 4K 20SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 38
系列: 89EB
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 11
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 616 (CN2011-ZH PDF)
13
AT89/83EB5114
4311C–8051–02/08
Description
The clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio from 40 to 60%.
Figure 4 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1÷2 to avoid glitches when switching from X2 to standard mode. Figure 5
shows the switching mode waveforms.
Figure 5. Mode Switching Waveforms
The X2 bit in the CKCON register (see Table 7 on page 18) allows to switch from 12
clock periods per instruction to 6 clock periods and vice versa.
Clock Prescaler
Before supplying the CPU and the peripherals, the main clock is divided by a factor from
2 to 32, as defined by the CKRL register (see Table 6 on page 18). The CPU needs from
12 to 16*12 clock periods per instruction. This allows:
to accept any cyclic ratio on XTAL1 input.
to reduce CPU power consumption.
Note:
The number of bits of the prescaler is optimized in order to provide a low power con-
sumption in low speed mode (see Section “Electrical Characteristics”, page 84).
Prescaler Divider on Reset
A hardware RESET selects the start oscillator depending on the RST1_OSC and
RST0_OSC bits contained on the Hardware Security Byte register (see Table 2 on page
15). It also selects the prescaler divider as follows:
CKRL = 8h: internal clock = OscOut / 16 (slow CPU speed at reset, thus lower
power consumption)
X2 = 0,
SEL_OSC1 and SEL_OSC0 bits selects OSCA, OSCB or OSCC, depending on the
value of the RST_OSC1 and RST_OSC0 configuration bits.
After Reset, any value between Fh down to 0h can be written by software into CKRL
sfr in order to divide frequency of the selected oscillator:
CKRL = 0h: minimum frequency = OscOut / 32
CKRL = Fh: maximum frequency = OscOut / 2
The frequency of the CPU and peripherals clock CkOut is related to the frequency of the
main oscillator OscOut by the following formula:
FCkOut = FOscOut / (32 - 2*CKRL)
XTAL1:2
XTAL1
CPU clock
X2 bit
X2 Mode
STD Mode
FOSC
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