參數(shù)資料
型號(hào)： AT89C5115-RATUM
廠商： Atmel
文件頁(yè)數(shù)： 8/113頁(yè)
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 16K 32VQFP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 1,250
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-LQFP
包裝： 托盤
配用： AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
2007-2011 Microchip Technology Inc.
DS70265E-page 105
dsPIC33FJ12MC201/202
8.1.3
PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 8-2.
The output of the primary oscillator or FRC, denoted as
‘FIN’, is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale
factor
‘N1’
is
selected
using
the
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25 to 40 MIPS.
For output ‘FIN’ on a primary oscillator, or FRC oscilla-
tor, the PLL output ‘FOSC’ is given by Equation 8-2.
EQUATION 8-2:
FOSC CALCULATION
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL.
If PLLPRE<4:0> = 0, then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
If PLLDIV<8:0> = 0x1E, then
M = 32. This yields a VCO output of 5 x 32 = 160
MHz, which is within the 100-200 MHz ranged
needed.
If PLLPOST<1:0> = 0, then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
EQUATION 8-3:
XT WITH PLL MODE
EXAMPLE
FIGURE 8-2:
dsPIC33FJ12MC201/202 PLL BLOCK DIAGRAM
FOSC
FIN
M
N1
N2
----------------------
=
FCY
FOSC
2
-------------
1
2
---
10000000
32
22
-------------------------------------
40 MIPS
==
=
0.8-8.0 MHz
Here(1)
100-200 MHz
Here(1)
Divide by
2, 4, 8
Divide by
2-513
Divide by
2-33
Source (Crystal, External Clock
PLLPRE
X
VCO
PLLDIV
PLLPOST
or Internal RC)
12.5-80 MHz
Here(1)
FOSC
Note 1:
This frequency range must be satisfied at all times.
FVCO
N1
M
N2
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AT89C51-16AA 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 4K Bytes Flash
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