參數(shù)資料
型號(hào): AT32AP7001-ALUT
廠商: Atmel
文件頁(yè)數(shù): 22/65頁(yè)
文件大小: 0K
描述: IC MCU 32BIT AVR32 208-LQFP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 180
系列: AVR®32 AP7
核心處理器: AVR
芯體尺寸: 32-位
速度: 150MHz
連通性: EBI/EMI,I²C,MMC,PS2,SPI,SSC,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 90
程序存儲(chǔ)器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: D/A 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-LQFP
包裝: 托盤
配用: ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATNGW100-ND - KIT AVR32 NETWORK GATEWAY
ATSTK1000-ND - KIT STARTER FOR AVR32AP7000
29
32015G–AVR32–09/09
AT32AP7001
The following expression represents what is computed by the VMUs in Vertical Filter Mode:
8.6
Output Pixel Inserter
The Output Pixel Inserter uses the OIM (Output Insertion Mode) field in the CONFIG register and
the destination pixel address given in the PICO operation instructions to decide which three of
the twelve possible OUTn pixels to write back the scaled and saturated results from the VMUs
to. The 22-bit results from each VMU is first scaled by performing an arithmetical right shift by
COEFF_FRAC_BITS in order to remove the fractional part of the results and obtain the integer
part. The integer part is then saturated to an unsigned 8-bit number in the range 0 to 255.
8.6.1
Planar Insertion Mode
In Planar Insertion Mode the destination pixel address OUTd specifies which pixel in each of the
registers OUTPIX0, OUTPIX1 and OUTPIX2 will be updated. VMUn writes to OUTPIXn. This
can be seen in Figure 8-5 on page 29 and Table 8-2 on page 47. This mode is useful when
transforming from one color space to another where the resulting color components should be
stored in separate images.
Figure 8-5.
Planar Pixel Insertion
VMU0_OUT
COEFF0_0 COEFF0_1 COEFF0_2
IN((x+0)%11)
IN((x+4)%11)
IN((x+8)%11)
OFFSET0 or VMU0_OUT
()
+
=
VMU1_OUT
COEFF1_0 COEFF1_1 COEFF1_2
IN((y+0)%11)
IN((y+4)%11)
IN((y+8)%11)
OFFSET1 or VMU1_OUT
()
+
=
VMU2_OUT
COEFF2_0 COEFF2_1 COEFF2_2
IN((z+0)%11)
IN((z+4)%11)
IN((z+8)%11)
OFFSET2 or VMU2_OUT
()
+
=
OUTPIX0
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUTPIX1
OUTPIX2
d = 0
d = 2
d = 1
d = 3
= VMU0
= VMU1
= VMU2
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