參數(shù)資料
型號： AT32AP7001-ALUT
廠商： Atmel
文件頁數(shù)： 10/65頁
文件大?。?/td> 0K
描述： IC MCU 32BIT AVR32 208-LQFP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 180
系列： AVR®32 AP7
核心處理器： AVR
芯體尺寸： 32-位
速度： 150MHz
連通性： EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB
外圍設(shè)備： AC'97，DMA，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 90
程序存儲器類型： ROMless
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器： D/A 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 208-LQFP
包裝： 托盤
配用： ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATNGW100-ND - KIT AVR32 NETWORK GATEWAY
ATSTK1000-ND - KIT STARTER FOR AVR32AP7000
18
32015G–AVR32–09/09
AT32AP7001
Figure 7-2.
The AVR32 AP Pipeline
.The follwing abbreviations are used in the figure:
IF1, IF2 - Instruction Fetch stage 1 and 2
ID - Instruction Decode
IS - Instruction Issue
A1, A2 - ALU stage 1 and 2
M1, M2 - Multiply stage 1 and 2
DA - Data Address calculation stage
D - Data cache access
WB - Writeback
7.2.2
AVR32B Microarchitecture Compliance
AVR32 AP implements an AVR32B microarchitecture. The AVR32B microarchitecture is tar-
geted at applications where interrupt latency is important. The AVR32B therefore implements
dedicated registers to hold the status register and return address for interrupts, exceptions and
supervisor calls. This information does not need to be written to the stack, and latency is there-
fore reduced. Additionally, AVR32B allows hardware shadowing of the registers in the register
file.
The scall, rete and rets instructions use the dedicated return status registers and return address
registers in their operation. No stack accesses are performed by these instructions.
7.2.3
Java Support
AVR32 AP provides Java hardware acceleration in the form of a Java Virtual Machine hardware
implementation. Refer to the AVR32 Java Technical Reference Manual for details.
7.2.4
Memory management
AVR32 AP implements a full MMU as specified by the AVR32 architecture. The page sizes pro-
vided are 1K, 4K, 64K and 1M. A 32-entry fully-associative common TLB is implemented, as well
as a 4-entry micro-ITLB and 8-entry micro-DTLB. Instruction and data accesses perform lookups
in the micro-TLBs. If the access misses in the micro-TLBs, an access in the common TLB is per-
formed. If this access misses, a page miss exception is issued.
IF2
ID
IS
A1
M1
M2
D
WB
Prefetch unit
Decode unit
ALU pipe
Multiply pipe
Load-store
pipe
DA
A2
IF1
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