參數(shù)資料
型號： CY2308SI-2
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： 3.3V Zero Delay Buffer
中文描述： 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝： 0.150 INCH, MS-012, SOIC-16
文件頁數(shù)： 8/17頁
文件大?。?/td> 503K
代理商： CY2308SI-2
CY2308
Document Number: 38-07146 Rev. *L
Page 16 of 17
Document History Page
Document Title: CY2308 3.3V Zero Delay Buffer
Document Number: 38-07146
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
**
110255
SZV
12/17/01
Changed from Specification number: 38-00528 to 38-07146
*A
118722
RGL
10/31/02
Added Note 1 in page 2.
*B
121832
RBI
12/14/02
Power up requirements added to Operating Conditions Information
*C
235854
RGL
06/24/04
Added Pb-free Devices
*D
310594
RGL
02/09/05
Removed obsolete parts in the ordering information table
Specified typical value for cycle-to-cycle jitter
*E
1344343
KVM/VED
08/20/07
Brought the Ordering Information Table up to date: removed three obsolete parts
and added two parts
Changed titles to tables that are specific to commercial and industrial temperature
ranges
*F
2568575
AESA
09/19/08
Updated template. Added Note “Not recommended for new designs.”
Changed IDD (PD mode) from 12.0 to 25.0
A for Commercial and Industrial
Temperature Devices
Deleted Duty Cycle parameters for Fout <50 MHz
Removed CY2308SI-4, CY2308SI-4T and CY2308SC-5HT.
*G
2632364
KVM
01/08/09
Corrected TSSOP package size (from 150 mil to 4.4 mm) in Ordering Information
table
*H
2673353
KVM/PYRS
03/13/09
Reverted IDD (PD mode) and Duty Cycle parameters back to the values in
revision *E:
Changed IDD (PD mode) from 25 to 12
A for commercial temperature devices
Added Duty Cycle parameters for Fout <50 MHz for commercial and industrial
devices.
*I
2897373
CXQ
03/22/10
Updated ordering information table.
Updated copyright section.
Updated package diagrams.
*J
2971365
BASH
07/06/10
Updated input to output skew and power down current number in Functional
Description, page 1
Update pin descriptions in ‘Pin Description’ column, Table1, page 2
Added ‘Input Frequency’ parameter and output frequency for –1H and –5H in
‘Switching Characteristics Table’ and removed footnote, page 4, 5, and 7.
Modified Description on page-1 and page-3 to make clear that user has to select
one of the outputs to drive feedback.
Added footnote in ‘Available CY2308 Configurations’ Table, page-3, for
clarification.
*K
3047133
CXQ
10/04/2010 Sunset Review. No change to datasheet from last revision.
*L
3055192
CXQ
10/11/2010 Removed part CY2308SXI–5H and CY2308SXI–5HI
相關(guān)PDF資料
PDF描述
CY2308SI-4 3.3V Zero Delay Buffer
CY2308 3.3V Zero Delay Buffer
CY2309AZI-1H 2309 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
CY23S09SXC-1T 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
CY2DP818ZXCT 2DP SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO38
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY2308SI-2[19] 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V Zero Delay Buffer
CY2308SI-2T 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R
CY2308SI-2T[19] 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V Zero Delay Buffer
CY2308SI-3 功能描述:IC CLK ZDB 8OUT 133MHZ 16SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
CY2308SI-3T 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R 制造商:Rochester Electronics LLC 功能描述:3.3VPLL ZERO DELAY CLOCK MULTIPLEXER SOIC 16 - Bulk
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