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參數(shù)資料
| 型號： | ASDP-21365WBBCZ-1A |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 14/52頁 |
| 文件大?。?/td> | 1320K |
| 代理商： | ASDP-21365WBBCZ-1A |
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Rev. A
|
Page 14 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
RSTOUT/CLKOUT O
Output only
Local Clock Out/Reset Out
. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin. The functionality can be switched
between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register.
The default is reset out.
Processor Reset
. Resets the ADSP-2136x to a known state. Upon deassertion, there is
a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
Test Clock (JTAG)
. Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processors.
Test Mode Select (JTAG)
. Used to control the test state machine. TMS has a 22.5 k
Ω
internal pull-up resistor.
Test Data Input (JTAG)
. Provides serial data for the boundary scan logic. TDI has a
22.5 k
Ω
internal pull-up resistor.
Test Data Output (JTAG)
. Serial scan output of the boundary scan path.
Test Reset (JTAG)
. Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-2136x. TRST has a
22.5 k
Ω
internal pull-up resistor.
Emulation Status
. Must be connected to the processor’s JTAG emulators target board
connector only. EMU has a 22.5 k
Ω
internal pull-up resistor.
Core Power Supply
. Nominally +1.2 V dc for the K, B grade models, and
1.0 V dc for the Y and W grade models, and supplies the processor’s core (13 pins).
I/O Power Supply
. Nominally +3.3 V dc (6 pins).
Analog Power Supply
. Nominally +1.2 V dc for the K, B grade models, and
1.0 V dc for the Y and W Grade models, and supplies the processor’s internal PLL (clock
generator). This pin has the same specifications as V
DDINT
, except that added filtering
circuitry is required.
For more information, see Power Supplies on Page 9.
Analog Power Supply Return
.
Power Supply Return
.
(54 pins)
RESET
I/A
Input only
TCK
I
Input only
3
TMS
I/S
(pu)
I/S
(pu)
O
I/A
(pu)
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Three-state
4
Three-state with
pull-up enabled
TDI
TDO
TRST
EMU
O (O/D)
(pu)
P
Three-state with
pull-up enabled
V
DDINT
V
DDEXT
A
VDD
P
P
A
VSS
GND
G
G
1
RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver with both output path and pull-up disabled.
4
Three-state is a three-state driver with pull-up disabled.
Table 4. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Description
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