參數(shù)資料
型號(hào)： ASDP-21365BBC-1AA
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁(yè)數(shù)： 19/52頁(yè)
文件大小： 1320K
代理商： ASDP-21365BBC-1AA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. A
|
Page 19 of 52
|
December 2006
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 12
.
Table 12. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing Requirements
t
RSTVDD
t
IVDDEVDD
t
CLKVDD
1
t
CLKRST
t
PLLRST
Min
Max
Unit
RESET Low Before V
DDINT
/V
DDEXT
On
V
DDINT
On Before V
DDEXT
CLKIN Valid After V
DDINT
/V
DDEXT
Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
0
–50
0
10
2
20
ns
ms
ms
μs
μs
+200
+200
Switching Characteristic
t
CORERST
Core Reset Deasserted After RESET Deasserted
4096t
CK
+ 2 t
CCLK
3,
4
1
Valid V
/V
assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of
milliseconds depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
4
The 4096 cycle count depends on t
SRST
specification in
Table 14
. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Figure 7. Power-Up Sequencing
CLKIN
RESET
t
RSTVDD
RSTOUT
V
DDEXT
V
DDINT
t
PLLRST
t
CLKRST
t
CLKVDD
t
IVDDEVDD
CLK_CFG1-0
t
CORERST
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