參數(shù)資料
型號： AS8510-ASST
廠商： ams
文件頁數(shù)： 16/47頁
文件大?。?/td> 0K
描述： IC BATTERY MANAGEMENT 20-SSOP
產(chǎn)品培訓(xùn)模塊： AS8510 Data Acquisition IC
標(biāo)準(zhǔn)包裝： 2,000
類型： 電池管理
輸入類型： 模擬，數(shù)字
輸出類型： 模擬，數(shù)字
接口： SPI 串行
電流 - 電源： 5mA
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 帶卷 (TR)
Revision 3.5
22 - 46
AS8510
Datasheet - Detailed Descr i p ti on
7.8 4-Wire Serial Port Interface
The SPI interface is used as interface between the AS8510 and an external micro-controller to configure the device and access the status
information. The micro-controller begins communication with the SPI which is configured as a slave. The SPI protocol is simple and the length of
each frame is an integer multiple of bytes except when a transmission is started. Each frame has 1 command bit, 7 address/configuration bits,
and one or more data bytes. The edge of CS and the level of SCLK during the start of a SPI transaction, determine the edge on which the data is
transferred from the SPI and the edge on which the data is sampled by the slave. Table 29 describes the setting of the transfer and sampling
edges of SCLK. Figure 9 shows the falling edge and rising edge for data transfer and data sampling respectively, when SCLK is HIGH on the
falling edge of CS.
Figure 9. Protocol for Serial Data Write with Length = 1
7.8.1 SPI Frame
A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of
bytes. Command is coded on the 1 first bit, while address is given on LSB 7 bits (see Table 30).
If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling),
the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
Table 29. CS and SCLK
CS
SCLK
Description
FALL
LOW
Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock.
FALL
HIGH
Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock.
ANY
Serial data transfer edge is unchanged.
Table 30. Command Bits
Command Bits
Register Address or Transmission Configuration
C0
A6
A5
A4
A3
A2
A1
A0
Table 31. Command Bits
C0
Command
<A6:A0>
Description
0
WRITE
ADDRESS
Writes data byte on the given starting address.
1
READ
ADDRESS
Read data byte from the given starting address.
CS
SCLK
SDI
SDO
0
A6
A5
A4
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D7
D6
Transfer edge
Sampling edge
Data D7 – D0 is moved
to Address A4..A0 here
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