
AS3515 V15
austriamicrosystems
Data Sheet, Confidential
www.austriamicrosystems.com
Revision 3.1
35
- 66
6.12 SYSTEM
6.12.1 General
The system block handles the power up and power down of the AS3515.
6.12.2 Power Up
The AS3515 powers up when on of the following condition is true:
High signal on the PWR_UP pin (>80ms, >1V)
Input voltage on the UVDD pin (USB plug in: >80ms, BVDD>3V, UVDD>4.5V)
Input voltage on the CHG_IN pin (charger plug in: >80ms, BVDD>3V, CHG_IN>4.0V)
To hold the chip in power up mode the PwrUpHld bit in the SYSTEM register (0x20h)is set.
6.12.3 Power Down
The chip automatically shuts off if one of the following conditions arises:
Clearing the PwrUpHld bit in SYSTEM register (0x20h)
I2C watchdog power down if enabled
BVDD drops below the minimum threshold voltage (2.6V)
Junction temperature reaches maximum threshold, set in SUPERVISOR register (0x24h)
High signal on the PWR_UP pin for more than 11s.
Figure 15 Power Up Timing
Power up from PwrUp, CHG_IN,
UVDD or RTCSUP pin
BVDD
rising with VBAT1 supply (DCDC3V)
VREF, IREF
rising with vdd_bandgap
QLDO1 & 2
AVDD & DVDD for internal supply
Enable Startup Sequence
EN LDO2 + DCDC
start sequencer with 1.2 MHz clock
VREF=ok
QLDO2=ok
Enable PVDD
Enable CVDD
+50ms
+52ms
+54ms
PowerGood = XRES
+56ms
Enable CPVDD
ams
AG
Technical
content
still
valid