
AS3515 V15
austriamicrosystems
Data Sheet, Confidential
www.austriamicrosystems.com
Revision 3.1
32
- 66
6.11 Charge-Pump Step-Down Converter
6.11.1 General
This converter will be used to supply the core voltage for a microprocessor.
Input Voltage CPVDD
Output Voltage 0.85 to 1.8 V
Voltage setting via P_CVDD and CVDDp<1:0> bits in 16 steps
regulated 2:1 charge pump with pulse skipping
scaleable switches according to BVDD
Bypass LDO for higher currents or lower battery voltages respectively
Driver strength: 50mA / 200mA with bypass LDO
Figure 13 Charge Pump Block Diagram
Mode_1
VBAT Length Reg.
Mode_2
CPVDD Length Reg.
Mode_3
ChPump Length Reg.
Charge-Pump
With ext. C-Fly
500kHz
2u2F
330nF
LDO4
3.56V
clamp
CN
CP
CVDD
CPVDD
BVDD
VB1V
2u2F
CVDD Regulator
6.11.2 Functional Description
To reduce the power consumption when using CVDDs below 1.8V, CPVDD is automatically set to 3.3V and can be further reduced to
3.1V if needed.
Table 32 CVDD programming
CPVDD
P_CVDD
CVDD
CPVDDp=0 CPVDDp=1
VSS
OFF
3.3V
3.1V
150k to VSS
1.0V
3.3V
3.1V
Open
1.2V
3.3V
3.1V
150k to DVDD
1.5V
3.3V
3.1V
DVDD
1.8V
3.56V
Additional the CVDD voltage can be trimmed with two register bits in the range of 0mV to -150mV
ams
AG
Technical
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