
AS3515 V15
austriamicrosystems
Data Sheet, Confidential
www.austriamicrosystems.com
Revision 3.1
23
- 66
Right ADC Register (10h)
Table 23 ADC_R Register
Bit
Name
Description
7,6
ADCmux
00: Stereo Microphone
01: Line_IN1
10: Line_IN2
11: Audio SUM
5
-
4..0
ADR_VOL
volume settings for right ADC input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
The register is R/W; default value is 00h
Left ADC Register (11h)
Table 24 ADC_L Register
Bit
Name
Description
7
AD_FS2
Divider selection for ADC clock
0: ADC sample clock is I2S LRCK / 2
1: ADC sample clock is I2S LRCK / 4
6
ADC_Mute_off 0: ADC input is set to mute
1: normal operation
5
-
4..0
ADL_VOL
Volume settings for left ADC input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
The register is R/W; default value is 00h
PLL Mode Register (1Dh)
Table 25 PLLMode Register
Bit
Name
Description
7..3
-
Not used
2,1
PLLmode<1:0> Sets the MCLK generation for different LRCK speeds:
00: LRCK: 24-48kHz
01: reserved
10: LRCK: 8-23kHz
11: reserved
0
-
Not used
The register is R/W; default value is 00h
ams
AG
Technical
content
still
valid