This read-only bit reflects the state of the interru" />
參數(shù)資料
型號： APMOTOR56F8000E
廠商： Freescale Semiconductor
文件頁數(shù)： 82/124頁
文件大?。?/td> 0K
描述： KIT DEMO MOTOR CTRL SYSTEM
標(biāo)準(zhǔn)包裝： 1
附件類型： 電機(jī)控制器
適用于相關(guān)產(chǎn)品： DEMO56F8013，DEMO56F8013-E
相關(guān)產(chǎn)品： MC56F8006VWL-ND - DSC 16K FLASH 32MHZ 28-SOIC
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MC56F8006VLC-ND - DSC 16K FLASH 32MHZ 32-LQFP
MC56F8002VWL-ND - DSC 12K FLASH 32MHZ 28-SOIC
DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013
MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP
MC56F8013VFAE-ND - IC DIGITAL SIGNAL CTLR 32-LQFP
更多...
56F8014 Technical Data, Rev. 11
60
Freescale Semiconductor
5.5.16.1
Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.5.16.2
Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being
sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service
routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
5.5.16.3
Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[6:0]) used at the time the last IRQ was taken. In the
case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when
the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.5.16.4
Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
0 = Normal operation (default)
1 = All interrupts disabled
Table 5-3 Interrupt Priority Encoding
IPIC_VALUE[1:0]
Current Interrupt
Priority Level
Required Nested
Exception Priority
00
No interrupt or SWILP
Priorities 0, 1, 2, 3
01
Priority 0
Priorities 1, 2, 3
10
Priority 1
Priorities 2, 3
11
Priority 2 or 3
Priority 3
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