ProASICPLUS Flash Family FPGAs v5.9 2-1 General Description Routing Resources
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� APA300-FGG256I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 13/178闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 300K 256-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 73728
杓稿叆/杓稿嚭鏁�(sh霉)锛� 186
闁€鏁�(sh霉)锛� 300000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)鐣�(d膩ng)鍓嶇13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)绗�109闋�(y猫)绗�110闋�(y猫)绗�111闋�(y猫)绗�112闋�(y猫)绗�113闋�(y猫)绗�114闋�(y猫)绗�115闋�(y猫)绗�116闋�(y猫)绗�117闋�(y猫)绗�118闋�(y猫)绗�119闋�(y猫)绗�120闋�(y猫)绗�121闋�(y猫)绗�122闋�(y猫)绗�123闋�(y猫)绗�124闋�(y猫)绗�125闋�(y猫)绗�126闋�(y猫)绗�127闋�(y猫)绗�128闋�(y猫)绗�129闋�(y猫)绗�130闋�(y猫)绗�131闋�(y猫)绗�132闋�(y猫)绗�133闋�(y猫)绗�134闋�(y猫)绗�135闋�(y猫)绗�136闋�(y猫)绗�137闋�(y猫)绗�138闋�(y猫)绗�139闋�(y猫)绗�140闋�(y猫)绗�141闋�(y猫)绗�142闋�(y猫)绗�143闋�(y猫)绗�144闋�(y猫)绗�145闋�(y猫)绗�146闋�(y猫)绗�147闋�(y猫)绗�148闋�(y猫)绗�149闋�(y猫)绗�150闋�(y猫)绗�151闋�(y猫)绗�152闋�(y猫)绗�153闋�(y猫)绗�154闋�(y猫)绗�155闋�(y猫)绗�156闋�(y猫)绗�157闋�(y猫)绗�158闋�(y猫)绗�159闋�(y猫)绗�160闋�(y猫)绗�161闋�(y猫)绗�162闋�(y猫)绗�163闋�(y猫)绗�164闋�(y猫)绗�165闋�(y猫)绗�166闋�(y猫)绗�167闋�(y猫)绗�168闋�(y猫)绗�169闋�(y猫)绗�170闋�(y猫)绗�171闋�(y猫)绗�172闋�(y猫)绗�173闋�(y猫)绗�174闋�(y猫)绗�175闋�(y猫)绗�176闋�(y猫)绗�177闋�(y猫)绗�178闋�(y猫)
ProASICPLUS Flash Family FPGAs
v5.9
2-1
General Description
Routing Resources
The routing structure of ProASICPLUS devices is designed
to provide high performance through a flexible four-
level hierarchy of routing resources: ultra-fast local
resources, efficient long-line resources, high-speed, very
long-line
resources,
and
high
performance
global
networks.
The ultra-fast local resources are dedicated lines that
allow the output of each tile to connect directly to every
input of the eight surrounding tiles (Figure 2-1).
The efficient long-line resources provide routing for
longer distances and higher fanout connections. These
resources vary in length (spanning 1, 2, or 4 tiles), run
both vertically and horizontally, and cover the entire
ProASICPLUS device (Figure 2-2 on page 2-2). Each tile can
drive signals onto the efficient long-line resources, which
can in turn access every input of every tile. Active buffers
are inserted automatically by routing software to limit
the loading effects due to distance and fanout.
The high-speed, very long-line resources, which span the
entire device with minimal delay, are used to route very
long or very high fanout nets. (Figure 2-3 on page 2-3).
The high-performance global networks are low-skew,
high fanout nets that are accessible from external pins or
from internal logic (Figure 2-4 on page 2-4). These nets
are typically used to distribute clocks, resets, and other
high fanout nets requiring a minimum skew. The global
networks are implemented as clock trees, and signals can
be introduced at any junction. These can be employed
hierarchically with signals accessing every input on all
tiles.
Figure 2-1 Ultra-Fast Local Resources
L
Inputs
Output
Ultra-Fast
Local Lines
(connects a tile to the
adjacent tile, I/O buffer,
or memory block)
L
LL
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A54SX16P-TQ176I IC FPGA SX 24K GATES 176-TQFP
A54SX16P-1TQ176 IC FPGA SX 24K GATES 176-TQFP
HMM44DRYF CONN EDGECARD 88POS DIP .156 SLD
AMM25DRMN CONN EDGECARD 50POS .156 WW
A54SX16P-1TQG176 IC FPGA SX 24K GATES 176-TQFP
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
APA300-FGG256M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 256FBGA - Trays
APA300-FGGB 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs
APA300-FGGES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs
APA300-FGGI 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs
APA300-FGGM 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC Flash Family FPGAs