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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� APA150-FG144
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 80/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 150K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 100
闁€鏁�(sh霉)锛� 150000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASICPLUS Flash Family FPGAs
4- 2
v5.9
v5.1
MIL-STD-883 was added to the datasheet.
N/A
VCC and VCCI were changed to VDDP.
N/A
v5.0
In the "208-Pin PQFP" table, the following pin numbers have been updated:
Pin Number
Function
24
I/O / GL2
30
I/O / GL1
In the "208-Pin CQFP" table, the following pin numbers have been updated:
Pin Number
Function
23
I/O / GLMX1
24
I/O / GL2
28
PPECL1 / Input
30
I/O / GL1
128
I/O / GL3
129
PPECL2 / Input
134
I/O / GL4
135
I/O / GLMX2
v4.1
In the "624-Pin CCGA/LGA" table, the following pin numbers have been updated:
Pin Number
Function
M6
I/O / GL2
M7
I/O / GLMX1
M19
I/O / GLMX2
M20
I/O / GL4
N5
PPECL1 / Input
N6
I/O / GL1
N20
I/O / GL3
N21
PPECL2 / Input
MIL-STD 883B data will be added into this datasheet after the MIL-STD 883B qualification is
complete.
Green packaging information in the "Ordering Information" section was updated.
The "Temperature Grade Offerings" table was updated for the CG624.
The 3.3 V column in Table 2-3 was updated.
The note was removed from Table 2-4 I/O Features.
The first bullet in the "ProASICPLUS Clock Management System" section was updated.
The first paragraph in the "Performance Retention" section was updated.
Mixed Voltage was removed from Table 2-20 Recommended Maximum Operating
Mixed Mode Voltage was removed from Table 2-22 and the Military/MIL-STD-883B column was
updated.
Previous version
Changes in current version (v5.9)
Page
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APA150-FG144A 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 150K 144-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
APA150-FG144I 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 150K 144-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
APA150-FG256 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 150K 256-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
APA150-FG256A 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 150K 256-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
APA150-FG256I 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 150K 256-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:ProASICPLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�