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鍨嬭櫉(h脿o)锛� APA150-BGG456
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 154/178闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
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妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 242
闁€鏁�(sh霉)锛� 150000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
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渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 456-PBGA锛�35x35锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-67
Asynchronous FIFO Read
Note: The plot shows the normal operation status.
Figure 2-40 Asynchronous FIFO Read
Table 2-63 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 鈥�55掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
ERDH, FRDH,
THRDH
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RB
鈫�
0.5
ns
Empty/full/thresh are invalid from the end
of hold until the new access is complete
ERDA
New EMPTY access from RB
鈫�
3.01
ns
FRDA
FULL
鈫� access from RB 鈫�
3.01
ns
ORDA
New DO access from RB
鈫�
7.5
ns
ORDH
Old DO valid from RB
鈫�
3.0
ns
RDCYC
Read cycle time
7.5
ns
RDWRS
WB
鈫�, clearing EMPTY, setup to
RB
鈫�
3.02
ns
Enabling the read operation
1.0
ns
Inhibiting the read operation
RDH
RB high phase
3.0
ns
Inactive
RDL
RB low phase
3.0
ns
Active
RPRDA
New RPE access from RB
鈫�
9.5
ns
RPRDH
Old RPE valid from RB
鈫�
4.0
ns
THRDA
EQTH or GETH access from RB
鈫�
4.5
ns
Notes:
1. At fast cycles, ERDA and FRDA = MAX (7.5 ns 鈥� RDL), 3.0 ns.
2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns 鈥� WRL), 3.0 ns.
RB = (RDB+RBLKB)
RPE
RDATA
EMPTY
EQTH, GETH
FULL
(Empty inhibits read)
Cycle Start
WB
tRDWRS
tERDH, tFRDH
tERDA, tFRDA
tTHRDH
tORDH
tRPRDH
tORDA
tRPRDA
tRDL
tRDH
tRPRDA
tRDL
tRDCYC
tRDH
tTHRDA
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ABM43DTMS CONN EDGECARD 86POS R/A .156 SLD
APA150-PQG208A IC FPGA PROASIC+ 150K 208-PQFP
ABM43DTBS CONN EDGECARD 86POS R/A .156 SLD
APA150-PQ208A IC FPGA PROASIC+ 150K 208-PQFP
ABM43DTAS CONN EDGECARD 86POS R/A .156 SLD
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