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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� APA150-BGG456
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 141/178闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA PROASIC+ 150K 456-PBGA
妯欐簴鍖呰锛� 24
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 242
闁€鏁�(sh霉)锛� 150000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 456-BBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 456-PBGA锛�35x35锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-55
Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 2-28 Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Table 2-52 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 鈥�55掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
OCA
New DO access from RCLKS
鈫�
7.5
ns
OCH
Old DO valid from RCLKS
鈫�
3.0
ns
RACH
RADDR hold from RCLKS
鈫�
0.5
ns
RACS
RADDR setup to RCLKS
鈫�
1.0
ns
RDCH
RDB hold from RCLKS
鈫�
0.5
ns
RDCS
RDB setup to RCLKS
鈫�
1.0
ns
RPCA
New RPE access from RCLKS
鈫�
9.5
ns
RPCH
Old RPE valid from RCLKS
鈫�
3.0
ns
RADDR
RPE
DO
RCLKS
RBD, RBLKB
New Valid Data Out
Cycle Start
Old Data Out
New Valid
Address
tRACS
tRDCS
tRDCH
tRACH
tOCH
tRPCH
tCMH
tOCA
tRPCA
tCCYC
tCML
鐩搁棞PDF璩囨枡
PDF鎻忚堪
ABM43DTMS CONN EDGECARD 86POS R/A .156 SLD
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ABM43DTBS CONN EDGECARD 86POS R/A .156 SLD
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