ProASICPLUS Flash Family FPGAs v5.9 2-61 Synchronous Write and Read to the Same " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� APA075-FGG144A
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 148/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 75K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷�(j矛)锛� 27648
杓稿叆/杓稿嚭鏁�(sh霉)锛� 100
闁€鏁�(sh霉)锛� 75000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-61
Synchronous Write and Read to the Same Location
Note: * New data is read if WCLKS
鈫� occurs before setup time. The data stored is read if WCLKS 鈫� occurs after hold time. The plot shows
the normal operation status.
Figure 2-34 Synchronous Write and Read to the Same Location
Table 2-58 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 鈥�55掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
WCLKRCLKS
WCLKS
鈫� to RCLKS 鈫� setup time
鈥� 0.1
ns
WCLKRCLKH
WCLKS
鈫� to RCLKS 鈫� hold time
7.0
ns
OCH
Old DO valid from RCLKS
鈫�
3.0
ns
OCA/OCH displayed for
Access Timed Output
OCA
New DO valid from RCLKS
鈫�
7.5
ns
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write
clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS
and RCLKS driven by the same design signal.
3. If WCLKS changes after the hold time, the data will be read.
4. A setup or hold time violation will result in unknown output data.
RCLKS
DO
WCLKS
t
WCLKRCLKH
New Data*
Last Cycle Data
t
WCLKRCLKS
t
OCH
t
CCYC
t
CMH
t
CML
t
OCA
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