ProASICPLUS Flash Family FPGAs 2- 56 v5.9 Synchronous SRAM Read, Pipeline Mode O" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� APA075-FGG144A
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 142/178闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA PROASIC+ 75K 144-FBGA
妯欐簴鍖呰锛� 160
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷堬細 27648
杓稿叆/杓稿嚭鏁�(sh霉)锛� 100
闁€鏁�(sh霉)锛� 75000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 144-LBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASICPLUS Flash Family FPGAs
2- 56
v5.9
Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 2-29 Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 2-53 TJ = 0掳C to 110掳C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = 0掳C to 150掳C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
OCA
New DO access from RCLKS
鈫�
2.0
ns
OCH
Old DO valid from RCLKS
鈫�
0.75
ns
RACH
RADDR hold from RCLKS
鈫�
0.5
ns
RACS
RADDR setup to RCLKS
鈫�
1.0
ns
RDCH
RDB hold from RCLKS
鈫�
0.5
ns
RDCS
RDB setup to RCLKS
鈫�
1.0
ns
RPCA
New RPE access from RCLKS
鈫�
4.0
ns
RPCH
Old RPE valid from RCLKS
鈫�
1.0
ns
RCLKS
RPE
DO
New Valid Data Out
Cycle Start
New RPE Out
RADDR
New Valid
Address
RDB, RBLKB
tRACS
tOCA
tRPCH
tOCH
tRPCA
tCML
tCMH
tCCYC
tRACH
tRDCH
tRDCS
Old Data Out
Old RPE Out
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APA075-FGG144I 鍔熻兘鎻忚堪:IC FPGA PROASIC+ 75K 144-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASICPLUS 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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