ProASICPLUS Flash Family FPGAs 2- 28 v5.9 Calculating Typical Power Dissipation " />
鍙冩暩璩囨枡
鍨嬭櫉锛� APA075-FGG144A
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩锛� 111/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 75K 144-FBGA
妯欐簴鍖呰锛� 160
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷堬細 27648
杓稿叆/杓稿嚭鏁革細 100
闁€鏁革細 75000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 144-LBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASICPLUS Flash Family FPGAs
2- 28
v5.9
Calculating Typical Power Dissipation
ProASICPLUS device power is calculated with both a static and an active component. The active component is a function
of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following
formula:
Total Power Consumption鈥擯total
Ptotal = Pdc + Pac
where:
Global Clock Contribution鈥擯clock
Pclock, the clock component of power dissipation, is given by the piece-wise model:
for R < 15000 the model is: (P1 + (P2*R) 鈥� (P7*R2)) * Fs (lightly-loaded clock trees)
for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees)
where:
Storage-Tile Contribution鈥擯storage
Pstorage, the storage-tile (Register) component of AC power dissipation, is given by
Pstorage = P5 * ms * Fs
where:
Pdc =
7 mW for the APA075
8 mW for the APA150
11 mW for the APA300
12 mW for the APA450
12 mW for the APA600
13 mW for the APA750
19 mW for the APA1000
Pdc includes the static components of PVDDP + PVDD + PAVDD
Pac =Pclock + Pstorage + Plogic + Poutputs + Pinputs + Ppll + Pmemory
P1
= 100 W/MHz is the basic power consumption of the clock tree per MHz of the clock
P2
= 1.3 W/MHz is the incremental power consumption of the clock tree per storage tile 鈥� also per MHz of the
clock
P7
= 0.00003 W/MHz is a correction factor for partially-loaded clock trees
P10
= 6850 W/MHz is the basic power consumption of the clock tree per MHz of the clock
P11
= 0.4 W/MHz is the incremental power consumption of the clock tree per storage tile 鈥� also per MHz of
the clock
R
= the number of storage tiles clocked by this clock
Fs
= the clock frequency
P5
=
1.1 W/MHz is the average power consumption of a storage tile per MHz of its output toggling rate.
The maximum output toggling rate is Fs/2.
ms
=
the number of storage tiles (Register) switching during each Fs cycle
Fs
=
the clock frequency
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