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參數(shù)資料
| 型號： | AN207 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | 12-ns DG611 Switch Family Combines Benefits of CMOS and DMOS Technologies |
| 中文描述： | 12納秒DG611開關(guān)系列組合的優(yōu)點CMOS和DMOS技術(shù) |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 149K |
| 代理商： | AN207 |
AN207
Vishay Siliconix
www.vishay.com FaxBack 408-970-5600
6-2
Document Number: 70605
03-Aug-99
FIGURE 2.
Typical Channel Block Diagram
V+
V
L
IN
Input Logic
Driver
V–
Level Translator
DMOS Switch
V–
D
S
The level translator provides level shifting of the 0 to 5 V logic
input to the V+ to V– voltage excursions needed to control the
MOSFET switch.
The driver stage acts as a buffer and provides current
amplification to quickly charge/discharge the MOSFET gate,
thus quickly turning the switch ON or OFF.
The switching element is an n-channel double-diffused
enhancement-mode MOSFET. DMOS FETs achieve very low
inter-electrode capacitance and high speed, thanks to their
lateral construction. To turn the switch ON, a voltage equal to
V+ is applied to the FET’s gate. This enhances the channel into
conduction.
The source and Drain terminals can stand up to 16 V with
respect to the substrate voltage (V–).
ESD protection diode pairs are connected from each logic
input, source, and drain pin to the V+ and V- power supply rails.
Optimized Characteristics
The DG611 family was designed to optimize the parameters
which are most important in high-speed applications.
Switching Speed
Discrete DMOS FETs such as the SD210 or SD5000 are well
known for their fast switching speeds. In fact, both specify a
t
d(on)
of 1 ns max. The DG611 family combines fast DMOS
switching elements with a low-power CMOS driver. These
devices are so fast that measuring their speed at final test
becomes
inductances/capacitances, generator’s rise and fall times)
conspire to slow things down. This is why the t
ON/
t
OFF
specifications on the data sheet are so loose (35 ns max).
a
challenge.
ATE
limitations
(lead
A typical device in a typical application is much faster than the
data-sheet specifications would indicate. A bench test circuit
reduced test fixture parasitics, while a low capacitance (3 pF)
FET probe was used to monitor the output voltage. Figure 3
shows that before the output starts to change there was a
propagation delay through the driver of about 8 ns. Once the
FET starts to turn on, the output voltage rises very fast. The
rise time was approximately 2 ns. Total t
ON
(50% Vin to 90%
Vout) was approximately 12 ns. Similarly at turn-off the
driver’s propagation delay appeared to be about 8 ns, the fall
time was about 5 ns. t
OFF
(50% V
IN
to 90% V
OUT
) was about
7 ns.
Reduced Switching Transients
By adding two dynamic compensation capacitors to the output
driver stage, charge injection glitches have been virtually
eliminated. For comparison purposes, Figure 4 illustrates the
typical charge injection characteristics for two Vishay Siliconix’
high-speed analog switches: DG271 and DG611. Note how
flat the DG611 characteristic is. This guarantees low charge
injection regardless of analog signal voltage.
Charge injection causes switching glitches both at turn-on and
at turn-off times. To evaluate and compare the switching
glitches produced by the DG611, the test circuit of Figure 5
was built. A 4-Vp-p triangular bipolar wave form was fed to the
switch input. On this wave form we wanted to cut some 0-V
notches as commanded by a pulse train. 100-ns pulses were
used to interrupt signal flow twice in every period letting the
output voltage to fall to 0 V.
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