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參數(shù)資料
| 型號(hào)： | AN207 |
| 廠(chǎng)商： | Vishay Intertechnology,Inc. |
| 英文描述： | 12-ns DG611 Switch Family Combines Benefits of CMOS and DMOS Technologies |
| 中文描述： | 12納秒DG611開(kāi)關(guān)系列組合的優(yōu)點(diǎn)CMOS和DMOS技術(shù) |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 149K |
| 代理商： | AN207 |
AN207
Vishay Siliconix
Document Number: 70605
03-Aug-99
www.vishay.com FaxBack 408-970-5600
6-1
12-ns DG611 Switch Family Combines Benefits of
CMOS and DMOS Technologies
The DG611, DG612, and DG613 are extremely low-power,
high-speed analog switches designed to optimize circuit
performance in high-speed switching applications. Each of
these devices integrates low-power CMOS drivers with
high-speed DMOS FETs. The resulting switches boast some
remarkable features: high speed, low power, low
on-resistance, low leakage, low charge injection and low
channel capacitance, all on the same device.
By combining both CMOS and DMOS technologies on a single
chip, the DG61X family avoids the tradeoffs inherent in other
high-speed analog switches, such as high power
consumption, high on-resistance, and high channel
capacitance. The DG61X family is likewise superior to DMOS
FETs, which are fast but highly sensitive to electrostatic
discharge, as well as requiring external drivers built with a
number of external discrete components.
This application note describes the new DG61X devices in
detail and provides a series of application hints which will help
you take full advantage of this fast new family in your designs.
Circuit Description
Each device has four independently controlled switches. The
DG611 and DG612 respond to opposite control logic. The
DG611 has a normally closed (NC) function while the DG612
is a normally open (NO) device.
The DG613 offers a complementary function. It contains two
NO and two NC switches. This versatile device can be
configured as two single-pole single-throw (SPDT), one
double-pole double-throw (DPDT), a “T” switch, two “L”
switches, and so forth.
As illustrated in Figure 2, each analog switch channel consists
of an input stage, followed by a level translator, a driver stage,
and an n-channel MOSFET.
The input stage is a CMOS inverter powered from V
L
. V
L
is the
logic power supply voltage (normally +5 V). As with any classic
CMOS inverter, control input pin impedance is very high and
essentially equivalent to the logic input pin capacitance
(approximately 5 pF). This pin does not draw current (except
for leakage) when in a steady state. To change states it is
necessary to charge or discharge this input capacitance,
which requires a short current pulse from the control logic gate.
S
1-4
IN
1-4
D
1-4
DG611
Normally Closed
S
1-4
IN
1-4
D
1-4
S
2, 3
IN
2, 3
D
2, 3
S
1, 4
IN
1, 4
D
1, 4
FIGURE 1.
Functional Diagrams (Typical Switch)
All Switches Shown for Logic “0” Inputs.
DG612
Normally Open
DG613
Complementary
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