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參數(shù)資料
| 型號： | AMIS30585C5852RG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODEM S-FSK HALFDUPLEX 28PLCC |
| 標準包裝： | 750 |
| 波特率： | 14.4k |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
AMIS30585
http://onsemi.com
11
Oscillator: Pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on
the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 8. OSCILLATOR
Parameter
Description
Condition
Min.
Max.
Unit
fCLK
Crystal frequency
(Note 8)
24 MHz
100 ppm
24 MHz
+100 ppm
Duty cycle with quartz connected
(Note 8)
30
70
%
Tstartup
Startup time
(Note 8)
50
Ms
CLXOUT
Maximum Capacitive load on XOUT
XIN used as clock input
50
pF
VILXOUT
Low input threshold voltage
XIN used as clock input
0.3 VDD
V
VIHXOUT
High input threshold voltage
XIN used as clock input
0.7 vdd
V
VOLXOUT
Low output voltage
XIN used as clock input, XOUT = 2 mA
0.3
V
VOHXOUT
High input voltage
XIN used as clock input
VDD0.3
V
8. For the design of the oscillator crystal parameters have been taken from the data sheet [8]. The series loss resistance for this type of crystal
is maximum 50 W. However the oscillator cell has been designed with some margin for series loss resistance up to 80 W.
Table 9. ZERO CROSSING DETECTOR AND 50/60HZ PLL: Pin M50HZ_IN
Parameter
Description
Condition
Min.
Max.
Unit
Imaxp
M50HZIN
Maximum peak input current
20
mA
Imaxavg
M50HZIN
Maximum average input current
during 1 ms
2
mA
VMAINS
Mains voltage (ms) range
With protection resistor at M50HZIN
90
550
V
VIRM50HZIN
Rising threshold level
(Note 9)
1.9
V
VIFM50HZIN
Falling threshold level
(Note 9)
0.9
V
VHY50HZIN
Hysteresis
(Note 9)
0.4
V
Flock50Hz
Lock range for 50 Hz (Note 10)
MAINS_FREQ = 0 (50 Hz)
45
55
Hz
Flock60Hz
Lock range for 60 Hz (Note 10)
MAINS_FREQ = 0 (60 Hz)
54
66
Hz
Tlock50Hz
Lock time (Note 10)
MAINS_FREQ = 0 (50 Hz)
10
S
Tlock60Hz
Lock time (Note 10)
MAINS_FREQ = 0 (60 Hz)
10
S
DF60Hz
Frequency variation without going
out of lock (Note 10)
MAINS_FREQ = 0 (50 Hz)
0.1
Hz/s
DF50Hz
Frequency variation without going
out of lock (Note 10)
MAINS_FREQ = 0 (60 Hz)
0.1
Hz/s
JitterCHIP_CLK
Jitter of CHIP_CLK (Note 10)
60
ms
9. Measured relative to VSS.
10.These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed
by the digital test patterns.
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