
20
Am79Q02/021/031 Data Sheet
SWITCHING CHARACTERISTICS over operating range (unless otherwise noted)
Min and max values are valid for all digital outputs with a 150 pF load, except CD1–C5 with a 30 pF load.
Microprocessor Interface
PCM Interface
PCLK not to exceed 8.192 MHz.
Pull-up resistors of 360
are attached to TSCA and TSCB.
No.
Symbol
Parameter
Min
Typ
Max
Units
1
tDCY
Data clock period
244
ns
2
tDCH
Data clock High pulse width
97
3
tDCL
Data clock Low pulse width
97
4
tDCR
Rise time of clock
25
5
tDCF
Fall time of clock
25
6
tICSS
Chip select setup time, Input state
70
tDCY –10
7
tICSH
Chip select hold time, Input state
0
tDCH –20
8
tICSL
Chip select pulse width, Input state
8tDCY
9
tICSO
Chip select off time, Input state (Note 1)
2.5
s
10
tIDS
Input data setup time
30
ns
11
tIDH
Input data hold time
30
12
tOLH
SLIC output latch valid
1000
13
tOCSS
Chip select setup time, Output state
70
tDCY –10
14
tOCSH
Chip select hold time, Output state
0
tDCH –20
15
tOCSL
Chip select pulse width, Output state
8tDCY
16
tOCSO
Chip select off time, Output state (Note 1)
2.5
s
17
tODD
Output data turn on delay (Note 2)
50
ns
18
tODH
Output data hold time
0
19
tODOF
Output data turn off delay
50
20
tODC
Output data valid
0
50
21
tRST
Reset pulse width
50
s
No.
Symbol
Parameter
Min
Typ
Max
Units
22
tPCY
PCM clock period (Note 3)
122
ns
23
tPCH
PCM clock High pulse width
48
24
tPCL
PCM clock Low pulse width
48
25
tPCF
Fall time of clock
15
26
tPCR
Rise time of clock
15
27
tFSS
FS setup time
25
tPCY–50
28
tFSH
FS hold time
50
30
tTSD
Delay to
TSC valid (Note 4)
5
80
31
tTSO
Delay to
TSC off (Note 4, 5)
5
80
32
tDXD
PCM data output delay
5
70
33
tDXH
PCM data output hold time
5
70
34
tDXZ
PCM data output delay to High-Z (Note 6)
5
70
35
tDRS
PCM data input setup time
25
36
tDRH
PCM data input hold time
5