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參數(shù)資料
| 型號(hào)： | AM79C973VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 73/304頁(yè) |
| 文件大?。?/td> | 2092K |
| 代理商： | AM79C973VCW |
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Am79C973/Am79C975
73
P R E L I M I N A R Y
ever, since IPG shrinkage below 4 ms will rarely be en-
countered on a correctly configured network, and since
the fragment size will be larger than the 4 ms blinding
window, the IPG counter will be reset by a worst case
IPG shrinkage/fragment scenario and the Am79C973/
Am79C975 controller will defer its transmission. If car-
rier is detected within the 4.0 to 6.0 ms IFS1 period, the
Am79C973/Am79C975 controller will not restart the
“
blinding
”
period, but only restart IFS1.
Collision Handling
Collision detection is performed and reported to the
MAC engine via the COL input pin.
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits
being transmitted, the MAC engine will abort the trans-
mission and append the jam sequence immediately.
The jam sequence is a 32-bit all zeros pattern.
The MAC engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to nor-
mal collisions (those within the slot time). Detection of
collision will cause the transmission to be rescheduled
to a time determined by the random backoff algorithm.
If a single retry was required, the 1 bit will be set in the
transmit frame status. If more than one retry was re-
quired, the MORE bit will be set. If all 16 attempts ex-
perienced collisions, the RTRY bit will be set (1 and
MORE will be clear), and the transmit message will be
flushed from the FIFO. If retries have been disabled by
setting the DRTY bit in CSR15, the MAC engine will
abandon transmission of the frame on detection of the
first collision. In this case, only the RTRY bit will be set
and the transmit message will be flushed from the
FIFO.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC engine will abort the transmission, append the
jam sequence, and set the LCOL bit. No retry attempt
will be scheduled on detection of a late collision, and
the transmit message will be flushed from the FIFO.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
use of a
“
truncated binary exponential backoff
”
algo-
rithm, which provides a controlled pseudo random
mechanism to enforce the collision backoff interval,
before retransmission is attempted.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“
At the end of enforcing a collision (jamming), the
CSMA/CD sublayer delays before attempting to re-
transmit the frame. The delay is an integer multiple
of slot time. The number of slot times to delay be-
fore the nth retransmission attempt is chosen as a
uniformly distributed random integer r in the range:
0
≤
r < 2k where k = min (n,10).
”
The Am79C973/Am79C975 controller provides an al-
ternative algorithm, which suspends the counting of the
slot time/IPG during the time that receive carrier sense
is detected. This aids in networks where large numbers
of nodes are present, and numerous nodes can be in
collision. It effectively accelerates the increase in the
backoff time in busy networks and allows nodes not in-
volved in the collision to access the channel, while the
colliding nodes await a reduction in channel activity.
Once channel activity is reduced, the nodes resolving
the collision time-out their slot time counters as normal.
This modified backoff algorithm is enabled when EMBA
(CSR3, bit 3) is set to 1.
Transmit Operation
The transmit operation and features of the Am79C973/
Am79C975 controller are controlled by programmable
options. The Am79C973/Am79C975 controller offers a
large transmit FIFO to provide frame buffering for in-
creased system latency, automatic retransmission with
no FIFO reload, and automatic transmit padding.
Transmit Function Programming
Automatic transmit features such as retry on collision,
FCS generation/transmission, and pad field insertion
can all be programmed to provide flexibility in the (re-)
transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the initializa-
tion block.
Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4.
The disable FCS generation/transmission feature can
be programmed as a static feature or dynamically on a
frame-by-frame basis.
Transmit FIFO Watermark (XMTFW) in CSR80 sets the
point at which the BMU requests more data from the
transmit buffers for the FIFO. A minimum of XMTFW
empty spaces must be available in the transmit FIFO
before the BMU will request the system bus in order to
transfer transmit frame data into the transmit FIFO.
Transmit Start Point (XMTSP) in CSR80 sets the point
when the transmitter actually attempts to transmit a
frame onto the media. A minimum of XMTSP bytes
must be written to the transmit FIFO for the current
frame before transmission of the current frame will be-
gin. (When automatically padded packets are being
sent, it is conceivable that the XMTSP is not reached
when all of the data has been transferred to the FIFO.
In this case, the transmission will begin when all of the
frame data has been placed into the transmit FIFO.)
The default value of XMTSP is 01b, meaning there has
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