參數(shù)資料
型號(hào)： AM79C973VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 130/304頁(yè)
文件大小： 2092K
代理商： AM79C973VCW
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130
Am79C973/Am79C975
P R E L I M I N A R Y
9
MFCO
Missed Frame Counter Overflow
is
set
by
the
Am79C975 controller when the
Missed Frame Counter (CSR112
and CSR113) has wrapped
around.
Am79C973/
When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
Read/Write accessible always.
MFCO is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
MFCO
is
H_RESET, S_RESET, or by set-
ting the STOP bit.
cleared
by
8
MFCOM
Missed Frame Counter Overflow
Mask. If MFCOM is set, the
MFCO bit will be masked and un-
able to set the INTR bit.
Read/Write accessible always.
MFCOM is set to 1 by H_RESET
or S_RESET and is not affected
by the STOP bit.
7
UINTCMD
User
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1.
UINTCMD will be cleared inter-
nally
after
the
Am79C975 controller has set
UINT to 1.
Interrupt
Command.
Am79C973/
Read/Write accessible always.
UINTCMD
is
H_RESET or S_RESET or by
setting the STOP bit.
cleared
by
6
UINT
User Interrupt. UINT is set by the
Am79C973/Am79C975 controller
after the host has issued a user
interrupt command by setting
UINTCMD (CSR4, bit 7) to 1.
Read/Write accessible always.
UINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
UINT
is
H_RESET or S_RESET or by
setting the STOP bit.
cleared
by
5
RCVCCO
Receive Collision Counter Over-
flow is set by the Am79C973/
Am79C975 controller when the
Receive
Collision
(CSR114 and CSR115) has
wrapped around.
Counter
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
Read/Write accessible always.
RCVCCO is cleared by the host
by writing a 1. Writing a 0 has no
effect. RCVCCO is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
4
RCVCCOM Receive Collision Counter Over-
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RCVCCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
3
TXSTRT
Transmit Start status is set by the
Am79C973/Am79C975 controller
whenever it begins transmission
of a frame.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
Read/Write accessible always.
TXSTRT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. TXSTRT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
2
TXSTRTM
Transmit Start Mask. If TX-
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
Read/Write accessible always.
TXSTRTM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
1-0
RES
Reserved locations. Written as
zeros and read as undefined.
CSR5: Extended Control and Interrupt 1
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
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