參數(shù)資料
型號(hào)： AM79C970AKCW
廠(chǎng)商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁(yè)數(shù)： 140/219頁(yè)
文件大?。?/td> 1065K
代理商： AM79C970AKCW
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AMD
P R E L I M I N A R Y
140
Am79C970A
Table 29. GPSI Mode Pin Configuration
PCnet-PCI II
Controller
Expansion
ROM Pin
PCnet-PCI II
Controller
GPSI Pin
PCnet-PCI II
Controller
Pin Number
C-LANCE
GPSI Pin
GPSI Function
GPSI I/O Type
Collision
I
CLSN
CLSN
81
ERD3
Receive Clock
I
RCLK
RXCLK
85
ERD1
Receive Data
I
RX
RXDAT
86
ERD0
Receive Enable
I
RENA
RXEN
83
ERD2
Transmit Clock
I
TCLK
TXCLK
80
ERD4
Transmit Data
O
TX
TXDAT
75
ERD7
Transmit Enable
O
TENA
TXEN
77
ERD6
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–5
RES
Reserved locations. Written as
ZEROs and read as undefined.
4
GPSIEN
General Purpose Serial Interface
Enable. This mode will recon-
figure some of the Expansion
ROM interface pins so that the
GPSI port is exposed. This
allows bypassing the MENDEC
and T-MAU logic. The PORTSEL
bits (CSR15, bits 8–7) must be
set to 10b in addition to program-
ming the GPSIEN bit in order to
select the GPSI port as the active
network port.
Read accessible always. Write
accessible when EN124 (CSR4,
bit 15) is set to ONE. GPSIEN
is cleared by H_RESET or
S_RESET and is not affected by
setting the STOP bit.
3
RPA
Runt Packet Accept. This bit
forces the PCnet-PCI II controller
to accept runt packets (packets
shorter than 64 bytes).
Read accessible always. Write
accessible when EN124 (CSR4,
bit 15) is set to ONE. RPA
is cleared by H_RESET or
S_RESET and is not affected by
setting the STOP bit.
2–0
RES
Reserved locations. Written as
ZEROs and read as undefined.
Bus Configuration Registers
The Bus Configuration Registers (BCRs) are used to
program the configuration of the bus interface and other
special features of the PCnet-PCI II controller that are
not related to the IEEE 8802-3 MAC functions. The
BCRs are accessed by first setting the appropriate
RAP value, and then by performing a slave access to
the BDP.
All BCR registers are 16 bits wide in Word I/O mode
(DWIO = 0, BCR18, bit 7) and 32 bits wide in DWord I/O
mode (DWIO = 1). The upper 16 bits of all BCR registers
are undefined when in DWord I/O mode. These bits
should be written as ZEROs and should be treated as
undefined when read. The default value given for any
BCR is the value in the register after H_RESET. Some
of these values may be changed shortly after H_RESET
when the contents of the external EEPROM is automati-
cally read in. With the exception of DWIO (BCR18, bit 7)
BCR register values are not affected by S_RESET.
None of the BCR register values are affected by the as-
sertion of the STOP bit.
Note that several registers have no default value. BCR0,
BCR1, BCR3, BCR8, BCR10–17 and BCR21 are re-
served and have undefined values. The content of
BCR2 is undefined until is has been first programmed
through the EEPROM read operation or a user register
write operation.
BCR0, BCR1, BCR16, BCR17 and BCR21 are registers
that are used by other devices in the PCnet family. Writ-
ing to these registers has no effect on the operation of
the PCnet-PCI II controller.
Writes to those registers marked as Reserved will have
no effect. Reads from these locations will produce
undefined values.
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PDF描述
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