參數(shù)資料
型號(hào): AM79C970AKCW
廠商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝: PLASTIC, QFP-132
文件頁(yè)數(shù): 104/219頁(yè)
文件大小: 1065K
代理商: AM79C970AKCW
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)當(dāng)前第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)
AMD
P R E L I M I N A R Y
104
Am79C970A
Table 19. I/O Map In Word I/O Mode (DWIO = 0)
Offset
No. of Bytes
Register
00h – 0Fh
16
APROM
10h
2
RDP
12h
2
RAP (shared by RDP
and BDP)
14h
2
Reset Register
16h
2
BDP
18h – 1Fh
8
Reserved
All I/O resources must be accessed in word quantities
and on word addresses. The Address PROM locations
can also be read in byte quantities. The only allowed
DWord operation is a write access to the RDP,
which switches the device to DWord I/O mode. A read
access other than listed in the table below will yield
undefined data, a write operation may cause unex-
pected reprogramming of the PCnet-PCI II controller
control registers.
Table 20. Legal I/O Accesses in Word I/O Mode (DWIO = 0)
AD[4:0]
BE
[3:0]
Type
Comment
0XX00
1110
RD
Byte Read of APROM Location 0h, 4h, 8h or Ch
0XX01
1101
RD
Byte Read of APROM Location 1h, 5h, 9h or Dh
0XX10
1011
RD
Byte Read of APROM Location 2h, 6h, Ah or Eh
0XX11
0111
RD
Byte Read of APROM Location 3h, 7h, Bh or Fh
0XX00
1100
RD
Word Read of APROM Locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h
and 9h or Ch and Dh
0XX10
0011
RD
Word Read of APROM Locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh
and Ah or Fh and Eh
10000
1100
RD
Word Read of RDP
10010
0011
RD
Word Read of RAP
10100
1100
RD
Word Read of Reset Register
10110
0011
RD
Word Read of BDP
0XX00
1100
WR
Word Write to APROM Locations 1h (MSB) and 0h (LSB), 5h and 4h, 8h
and 9h or Ch and Dh
0XX10
0011
WR
Word Write to APROM Locations 3h (MSB) and 2h (LSB), 7h and 6h, Bh
and Ah or Fh and Eh
10000
1100
WR
Word Write to RDP
10010
0011
WR
Word Write to RAP
10100
1100
Word Write to Reset Register
10110
0011
WR
Word Write to BDP
10000
0000
WR
DWord Write to RDP, switches Device to DWord I/O Mode
Double Word I/O Mode
The PCnet-PCI II controller can be configured to oper-
ate in DWord (32bit) I/O mode. The software can invoke
the DWIO mode by performing a DWord write access to
the I/O location at offset 10h (RDP). The data of the write
access must be such that it does not affect the intended
operation of the PCnet-PCI II controller. Setting the de-
vice into 32-bit I/O mode is usually the first operation af-
ter H_RESET or S_RESET. The RAP register will point
to CSR0 at that time. Writing a value of ZERO to CSR0
is a save operation. DWIO (BCR18, bit 7) will be set to
ONE as indicating that the PCnet-PCI II controller oper-
ates in 32-bit I/O mode.
Note that even though the I/O resource mapping
changes when the I/O mode setting changes, the RDP
location offset is the same for both modes. Once the
DWIO bit has been set to ONE, only H_RESET or
S_RESET can clear it to ZERO. The DWIO mode set-
ting is unaffected by setting the STOP bit.
The table below shows how the 32 bytes of address
space are used in DWord I/O mode.
相關(guān)PDF資料
PDF描述
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C971VCW PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AVC 制造商:Advanced Micro Devices 功能描述:
AM79C970AVC\\W 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:
AM79C970AVC\W 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:AMD 功能描述:
AM79C970AVC-G 制造商:Rochester Electronics LLC 功能描述:
AM79C970AVCW 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product